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[Instrumentation] Support verifying machine function (llvm#90931)
We need it to test isel related passes. Currently `verifyMachineFunction` is incomplete (no LiveIntervals support), but is enough for testing isel pass, will migrate to complete `MachineVerifierPass` in future.
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9 files changed

+138
-57
lines changed

9 files changed

+138
-57
lines changed

‎llvm/include/llvm/Passes/MachinePassRegistry.def

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,7 @@ MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
128128
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
129129
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
130130
RequireAllMachineFunctionPropertiesPass())
131+
MACHINE_FUNCTION_PASS("trigger-verifier-error", TriggerVerifierErrorPass())
131132
#undef MACHINE_FUNCTION_PASS
132133

133134
// After a pass is converted to new pass manager, its entry should be moved from

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 29 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -5075,6 +5075,8 @@ MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) {
50755075
auto &MIB = Builder;
50765076

50775077
bool UseNPQ = false;
5078+
bool UsePreShift = false;
5079+
bool UsePostShift = false;
50785080
SmallVector<Register, 16> PreShifts, PostShifts, MagicFactors, NPQFactors;
50795081

50805082
auto BuildUDIVPattern = [&](const Constant *C) {
@@ -5087,27 +5089,28 @@ MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) {
50875089

50885090
// Magic algorithm doesn't work for division by 1. We need to emit a select
50895091
// at the end.
5090-
// TODO: Use undef values for divisor of 1.
5091-
if (!Divisor.isOne()) {
5092-
5093-
// UnsignedDivisionByConstantInfo doesn't work correctly if leading zeros
5094-
// in the dividend exceeds the leading zeros for the divisor.
5095-
UnsignedDivisionByConstantInfo magics =
5096-
UnsignedDivisionByConstantInfo::get(
5097-
Divisor, std::min(KnownLeadingZeros, Divisor.countl_zero()));
5098-
5099-
Magic = std::move(magics.Magic);
5100-
5101-
assert(magics.PreShift < Divisor.getBitWidth() &&
5102-
"We shouldn't generate an undefined shift!");
5103-
assert(magics.PostShift < Divisor.getBitWidth() &&
5104-
"We shouldn't generate an undefined shift!");
5105-
assert((!magics.IsAdd || magics.PreShift == 0) && "Unexpected pre-shift");
5106-
PreShift = magics.PreShift;
5107-
PostShift = magics.PostShift;
5108-
SelNPQ = magics.IsAdd;
5092+
if (Divisor.isOne()) {
5093+
PreShifts.push_back(MIB.buildUndef(ScalarShiftAmtTy).getReg(0));
5094+
MagicFactors.push_back(MIB.buildUndef(ScalarTy).getReg(0));
5095+
NPQFactors.push_back(MIB.buildUndef(ScalarTy).getReg(0));
5096+
PostShifts.push_back(MIB.buildUndef(ScalarShiftAmtTy).getReg(0));
5097+
return true;
51095098
}
51105099

5100+
UnsignedDivisionByConstantInfo magics = UnsignedDivisionByConstantInfo::get(
5101+
Divisor, std::min(KnownLeadingZeros, Divisor.countl_zero()));
5102+
5103+
Magic = std::move(magics.Magic);
5104+
5105+
assert(magics.PreShift < Divisor.getBitWidth() &&
5106+
"We shouldn't generate an undefined shift!");
5107+
assert(magics.PostShift < Divisor.getBitWidth() &&
5108+
"We shouldn't generate an undefined shift!");
5109+
assert((!magics.IsAdd || magics.PreShift == 0) && "Unexpected pre-shift");
5110+
PreShift = magics.PreShift;
5111+
PostShift = magics.PostShift;
5112+
SelNPQ = magics.IsAdd;
5113+
51115114
PreShifts.push_back(
51125115
MIB.buildConstant(ScalarShiftAmtTy, PreShift).getReg(0));
51135116
MagicFactors.push_back(MIB.buildConstant(ScalarTy, Magic).getReg(0));
@@ -5119,6 +5122,8 @@ MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) {
51195122
PostShifts.push_back(
51205123
MIB.buildConstant(ScalarShiftAmtTy, PostShift).getReg(0));
51215124
UseNPQ |= SelNPQ;
5125+
UsePreShift |= PreShift != 0;
5126+
UsePostShift |= magics.PostShift != 0;
51225127
return true;
51235128
};
51245129

@@ -5143,7 +5148,9 @@ MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) {
51435148
}
51445149

51455150
Register Q = LHS;
5146-
Q = MIB.buildLShr(Ty, Q, PreShift).getReg(0);
5151+
5152+
if (UsePreShift)
5153+
Q = MIB.buildLShr(Ty, Q, PreShift).getReg(0);
51475154

51485155
// Multiply the numerator (operand 0) by the magic value.
51495156
Q = MIB.buildUMulH(Ty, Q, MagicFactor).getReg(0);
@@ -5161,7 +5168,8 @@ MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) {
51615168
Q = MIB.buildAdd(Ty, NPQ, Q).getReg(0);
51625169
}
51635170

5164-
Q = MIB.buildLShr(Ty, Q, PostShift).getReg(0);
5171+
if (UsePostShift)
5172+
Q = MIB.buildLShr(Ty, Q, PostShift).getReg(0);
51655173
auto One = MIB.buildConstant(Ty, 1);
51665174
auto IsOne = MIB.buildICmp(
51675175
CmpInst::Predicate::ICMP_EQ,

‎llvm/lib/Passes/PassBuilder.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,7 @@
9393
#include "llvm/CodeGen/MIRPrinter.h"
9494
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
9595
#include "llvm/CodeGen/MachinePassManager.h"
96+
#include "llvm/CodeGen/MachineRegisterInfo.h"
9697
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
9798
#include "llvm/CodeGen/SafeStack.h"
9899
#include "llvm/CodeGen/SelectOptimize.h"
@@ -363,6 +364,14 @@ class TriggerVerifierErrorPass
363364
return PreservedAnalyses::none();
364365
}
365366

367+
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &) {
368+
// Intentionally create a virtual register and set NoVRegs property.
369+
auto &MRI = MF.getRegInfo();
370+
MRI.createGenericVirtualRegister(LLT::scalar(8));
371+
MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
372+
return PreservedAnalyses::all();
373+
}
374+
366375
static StringRef name() { return "TriggerVerifierErrorPass"; }
367376
};
368377

‎llvm/lib/Passes/StandardInstrumentations.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1487,6 +1487,17 @@ void VerifyInstrumentation::registerCallbacks(
14871487
"\"{0}\", compilation aborted!",
14881488
P));
14891489
}
1490+
1491+
// TODO: Use complete MachineVerifierPass.
1492+
if (auto *MF = unwrapIR<MachineFunction>(IR)) {
1493+
if (DebugLogging)
1494+
dbgs() << "Verifying machine function " << MF->getName() << '\n';
1495+
verifyMachineFunction(
1496+
formatv("Broken machine function found after pass "
1497+
"\"{0}\", compilation aborted!",
1498+
P),
1499+
*MF);
1500+
}
14901501
}
14911502
});
14921503
}

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll

Lines changed: 64 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -169,17 +169,17 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
169169
;
170170
; GISEL-LABEL: combine_vec_udiv_nonuniform4:
171171
; GISEL: // %bb.0:
172-
; GISEL-NEXT: adrp x8, .LCPI4_2
173-
; GISEL-NEXT: adrp x9, .LCPI4_0
174-
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI4_2]
175-
; GISEL-NEXT: adrp x8, .LCPI4_1
176-
; GISEL-NEXT: ldr q4, [x9, :lo12:.LCPI4_0]
177-
; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI4_1]
172+
; GISEL-NEXT: mov w8, #171 // =0xab
173+
; GISEL-NEXT: fmov s1, w8
174+
; GISEL-NEXT: adrp x8, .LCPI4_0
175+
; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI4_0]
176+
; GISEL-NEXT: mov w8, #7 // =0x7
178177
; GISEL-NEXT: umull2 v2.8h, v0.16b, v1.16b
179178
; GISEL-NEXT: umull v1.8h, v0.8b, v1.8b
179+
; GISEL-NEXT: shl v3.16b, v3.16b, #7
180180
; GISEL-NEXT: uzp2 v1.16b, v1.16b, v2.16b
181-
; GISEL-NEXT: neg v2.16b, v3.16b
182-
; GISEL-NEXT: shl v3.16b, v4.16b, #7
181+
; GISEL-NEXT: fmov s2, w8
182+
; GISEL-NEXT: neg v2.16b, v2.16b
183183
; GISEL-NEXT: ushl v1.16b, v1.16b, v2.16b
184184
; GISEL-NEXT: sshr v2.16b, v3.16b, #7
185185
; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b
@@ -217,25 +217,66 @@ define <8 x i16> @pr38477(<8 x i16> %a0) {
217217
;
218218
; GISEL-LABEL: pr38477:
219219
; GISEL: // %bb.0:
220-
; GISEL-NEXT: adrp x8, .LCPI5_3
221-
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI5_3]
222-
; GISEL-NEXT: adrp x8, .LCPI5_2
223-
; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI5_2]
224-
; GISEL-NEXT: adrp x8, .LCPI5_0
225-
; GISEL-NEXT: umull2 v2.4s, v0.8h, v1.8h
220+
; GISEL-NEXT: mov w8, #4957 // =0x135d
221+
; GISEL-NEXT: mov w9, #16385 // =0x4001
222+
; GISEL-NEXT: fmov s1, w8
223+
; GISEL-NEXT: mov w8, #57457 // =0xe071
224+
; GISEL-NEXT: fmov s4, w9
225+
; GISEL-NEXT: fmov s2, w8
226+
; GISEL-NEXT: mov w8, #4103 // =0x1007
227+
; GISEL-NEXT: mov w9, #35545 // =0x8ad9
228+
; GISEL-NEXT: fmov s5, w9
229+
; GISEL-NEXT: mov w9, #2048 // =0x800
230+
; GISEL-NEXT: mov v1.h[1], v1.h[0]
231+
; GISEL-NEXT: fmov s6, w9
232+
; GISEL-NEXT: adrp x9, .LCPI5_0
233+
; GISEL-NEXT: mov v1.h[2], v2.h[0]
234+
; GISEL-NEXT: fmov s2, w8
235+
; GISEL-NEXT: mov w8, #32768 // =0x8000
236+
; GISEL-NEXT: fmov s3, w8
237+
; GISEL-NEXT: mov w8, #0 // =0x0
238+
; GISEL-NEXT: mov v1.h[3], v2.h[0]
239+
; GISEL-NEXT: mov v2.h[1], v3.h[0]
240+
; GISEL-NEXT: mov v1.h[4], v4.h[0]
241+
; GISEL-NEXT: fmov s4, w8
242+
; GISEL-NEXT: mov w8, #6 // =0x6
243+
; GISEL-NEXT: mov v2.h[2], v4.h[0]
244+
; GISEL-NEXT: mov v1.h[5], v5.h[0]
245+
; GISEL-NEXT: fmov s5, w8
246+
; GISEL-NEXT: mov w8, #2115 // =0x843
247+
; GISEL-NEXT: mov v2.h[3], v4.h[0]
248+
; GISEL-NEXT: mov v7.h[1], v5.h[0]
249+
; GISEL-NEXT: mov v1.h[6], v6.h[0]
250+
; GISEL-NEXT: fmov s6, w8
251+
; GISEL-NEXT: mov w8, #12 // =0xc
252+
; GISEL-NEXT: mov v2.h[4], v4.h[0]
253+
; GISEL-NEXT: mov v7.h[2], v5.h[0]
254+
; GISEL-NEXT: mov v1.h[7], v6.h[0]
255+
; GISEL-NEXT: fmov s6, w8
256+
; GISEL-NEXT: mov w8, #14 // =0xe
257+
; GISEL-NEXT: fmov s16, w8
258+
; GISEL-NEXT: mov w8, #4 // =0x4
259+
; GISEL-NEXT: mov v2.h[5], v4.h[0]
260+
; GISEL-NEXT: mov v7.h[3], v6.h[0]
261+
; GISEL-NEXT: umull2 v6.4s, v0.8h, v1.8h
226262
; GISEL-NEXT: umull v1.4s, v0.4h, v1.4h
227-
; GISEL-NEXT: uzp2 v1.8h, v1.8h, v2.8h
228-
; GISEL-NEXT: sub v2.8h, v0.8h, v1.8h
229-
; GISEL-NEXT: umull2 v4.4s, v2.8h, v3.8h
230-
; GISEL-NEXT: umull v2.4s, v2.4h, v3.4h
231-
; GISEL-NEXT: ldr d3, [x8, :lo12:.LCPI5_0]
232-
; GISEL-NEXT: adrp x8, .LCPI5_1
233-
; GISEL-NEXT: ushll v3.8h, v3.8b, #0
263+
; GISEL-NEXT: mov v2.h[6], v4.h[0]
264+
; GISEL-NEXT: mov v7.h[4], v16.h[0]
265+
; GISEL-NEXT: uzp2 v1.8h, v1.8h, v6.8h
266+
; GISEL-NEXT: mov v2.h[7], v3.h[0]
267+
; GISEL-NEXT: mov v7.h[5], v5.h[0]
268+
; GISEL-NEXT: ldr d5, [x9, :lo12:.LCPI5_0]
269+
; GISEL-NEXT: sub v3.8h, v0.8h, v1.8h
270+
; GISEL-NEXT: mov v7.h[6], v4.h[0]
271+
; GISEL-NEXT: umull2 v4.4s, v3.8h, v2.8h
272+
; GISEL-NEXT: umull v2.4s, v3.4h, v2.4h
273+
; GISEL-NEXT: fmov s3, w8
274+
; GISEL-NEXT: mov v7.h[7], v3.h[0]
234275
; GISEL-NEXT: uzp2 v2.8h, v2.8h, v4.8h
235-
; GISEL-NEXT: ldr q4, [x8, :lo12:.LCPI5_1]
276+
; GISEL-NEXT: ushll v3.8h, v5.8b, #0
236277
; GISEL-NEXT: shl v3.8h, v3.8h, #15
237278
; GISEL-NEXT: add v1.8h, v2.8h, v1.8h
238-
; GISEL-NEXT: neg v2.8h, v4.8h
279+
; GISEL-NEXT: neg v2.8h, v7.8h
239280
; GISEL-NEXT: ushl v1.8h, v1.8h, v2.8h
240281
; GISEL-NEXT: sshr v2.8h, v3.8h, #15
241282
; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -228,16 +228,16 @@ body: |
228228
; CHECK: liveins: $q0
229229
; CHECK-NEXT: {{ $}}
230230
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
231-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
232-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 -85
233-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 7
234-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C1]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
235-
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
231+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -85
232+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 7
233+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
234+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
235+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C1]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
236236
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<16 x s8>) = G_UMULH [[COPY]], [[BUILD_VECTOR]]
237237
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<16 x s8>) = G_LSHR [[UMULH]], [[BUILD_VECTOR1]](<16 x s8>)
238-
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
239-
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
240-
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s1>) = G_BUILD_VECTOR [[C3]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1)
238+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
239+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
240+
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s1>) = G_BUILD_VECTOR [[C2]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1)
241241
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(<16 x s8>) = G_SELECT [[BUILD_VECTOR2]](<16 x s1>), [[COPY]], [[LSHR]]
242242
; CHECK-NEXT: $q0 = COPY [[SELECT]](<16 x s8>)
243243
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -264,6 +264,7 @@ body: |
264264
; CHECK: liveins: $q0
265265
; CHECK-NEXT: {{ $}}
266266
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
267+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
267268
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
268269
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 4957
269270
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
@@ -277,9 +278,9 @@ body: |
277278
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 2048
278279
; CHECK-NEXT: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 2115
279280
; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
280-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C1]](s16), [[C4]](s16), [[C5]](s16), [[C7]](s16), [[C9]](s16), [[C10]](s16), [[C11]](s16)
281-
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C2]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C2]](s16)
282-
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C3]](s16), [[C3]](s16), [[C6]](s16), [[C8]](s16), [[C3]](s16), [[C]](s16), [[C12]](s16)
281+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[C1]](s16), [[C4]](s16), [[C5]](s16), [[C7]](s16), [[C9]](s16), [[C10]](s16), [[C11]](s16)
282+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[C2]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C2]](s16)
283+
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[C3]](s16), [[C3]](s16), [[C6]](s16), [[C8]](s16), [[C3]](s16), [[C]](s16), [[C12]](s16)
283284
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[COPY]], [[BUILD_VECTOR]]
284285
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY]], [[UMULH]]
285286
; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[SUB]], [[BUILD_VECTOR1]]

‎llvm/test/CodeGen/MIR/X86/machine-verifier.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
2-
# This test ensures that the MIR parser runs the machine verifier after parsing.
2+
# This test ensures that the VerifyInstrumentation works for machine function.
33

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--- |
55

‎llvm/test/tools/llc/new-pm/verify.mir

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: not --crash llc -mtriple=x86_64-pc-linux-gnu -debug-pass-manager -passes='module(function(machine-function(trigger-verifier-error)))' -filetype=null %s 2>&1 | FileCheck %s
2+
3+
# CHECK: Verifying machine function f
4+
# CHECK: Broken machine function found after pass "TriggerVerifierErrorPass"
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---
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name: f
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body: |
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bb.0:
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RET 0
10+
...

‎llvm/tools/llc/NewPMDriver.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ int llvm::compileModuleWithNewPM(
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MachineModuleInfo MMI(&LLVMTM);
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PassInstrumentationCallbacks PIC;
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StandardInstrumentations SI(Context, Opt.DebugPM);
118+
StandardInstrumentations SI(Context, Opt.DebugPM, !NoVerify);
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SI.registerCallbacks(PIC);
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registerCodeGenCallback(PIC, LLVMTM);
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