-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathCPU.qsf
154 lines (152 loc) · 9.96 KB
/
CPU.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 15:23:41 January 27, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# CPU_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C16F484C6
set_global_assignment -name TOP_LEVEL_ENTITY datapath_new
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:23:41 JANUARY 27, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ns" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH datapath_new_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME not_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id not_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id not_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME not_new_tb -section_id not_new_tb
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_NAME and_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id and_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id and_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME and_new_tb -section_id and_new_tb
set_global_assignment -name EDA_TEST_BENCH_NAME or_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id or_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME or_new_tb -section_id or_new_tb
set_global_assignment -name EDA_TEST_BENCH_NAME fulladder_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id fulladder_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME fulladder_new_tb -section_id fulladder_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id or_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id fulladder_new_tb
set_global_assignment -name EDA_TEST_BENCH_NAME div_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id div_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id div_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME div_new_tb -section_id div_new_tb
set_global_assignment -name VERILOG_FILE register.v
set_global_assignment -name VERILOG_FILE bus.v
set_global_assignment -name VERILOG_FILE encoder.v
set_global_assignment -name VERILOG_FILE busMux.v
set_global_assignment -name VERILOG_FILE MDR_unit.v
set_global_assignment -name VERILOG_FILE MDR.v
set_global_assignment -name VERILOG_FILE MDMux.v
set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name VERILOG_FILE and_new.v
set_global_assignment -name VERILOG_FILE or_new.v
set_global_assignment -name VERILOG_FILE not_new.v
set_global_assignment -name VERILOG_FILE fulladder_new.v
set_global_assignment -name VERILOG_FILE add_new.v
set_global_assignment -name VERILOG_FILE sub_new.v
set_global_assignment -name VERILOG_FILE neg_new.v
set_global_assignment -name VERILOG_FILE mul_new.v
set_global_assignment -name VERILOG_FILE div_new.v
set_global_assignment -name VERILOG_FILE binary_shift_left.v
set_global_assignment -name VERILOG_FILE binary_shift_right.v
set_global_assignment -name VERILOG_FILE rotate_left.v
set_global_assignment -name VERILOG_FILE rotate_right.v
set_global_assignment -name VERILOG_FILE and_new_tb.v
set_global_assignment -name VERILOG_FILE or_new_tb.v
set_global_assignment -name VERILOG_FILE not_new_tb.v
set_global_assignment -name VERILOG_FILE fulladder_new_tb.v
set_global_assignment -name VERILOG_FILE div_new_tb.v
set_global_assignment -name VERILOG_FILE add_new_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME add_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id add_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id add_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME add_new_tb -section_id add_new_tb
set_global_assignment -name VERILOG_FILE sub_new_tb.v
set_global_assignment -name VERILOG_FILE neg_new_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME sub_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sub_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id sub_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sub_new_tb -section_id sub_new_tb
set_global_assignment -name EDA_TEST_BENCH_NAME neg_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id neg_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id neg_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME neg_new_tb -section_id neg_new_tb
set_global_assignment -name VERILOG_FILE mul_new_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME mul_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id mul_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id mul_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME mul_new_tb -section_id mul_new_tb
set_global_assignment -name VERILOG_FILE register_tb.v
set_global_assignment -name VERILOG_FILE register_64_bits.v
set_global_assignment -name VERILOG_FILE bidirectionalBus.v
set_global_assignment -name VERILOG_FILE PC_reg.v
set_global_assignment -name VERILOG_FILE datapath_new.v
set_global_assignment -name EDA_TEST_BENCH_NAME datapath_new_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id datapath_new_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id datapath_new_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME datapath_new_tb -section_id datapath_new_tb
set_global_assignment -name VERILOG_FILE datapath_new_tb.v
set_global_assignment -name VERILOG_FILE alu_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME alu_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id alu_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id alu_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME alu_tb -section_id alu_tb
set_global_assignment -name VERILOG_FILE shift_right_arithmetic.v
set_global_assignment -name VERILOG_FILE shift_right_arithmetic_tb.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_FILE not_new_tb.v -section_id not_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE and_new_tb.v -section_id and_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE or_new_tb.v -section_id or_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE fulladder_new_tb.v -section_id fulladder_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE div_new_tb.v -section_id div_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE add_new_tb.v -section_id add_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE sub_new_tb.v -section_id sub_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE neg_new_tb.v -section_id neg_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE mul_new_tb.v -section_id mul_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE datapath_new_tb.v -section_id datapath_new_tb
set_global_assignment -name EDA_TEST_BENCH_FILE alu_tb.v -section_id alu_tb
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top