encoder_tb.v.bak

`timescale 1ns/1ps

module encoder_tb;

//inputs and outputs
reg r0out, r1out, r2out, r3out, r4out, r5out, r6out, r7out, r8out, r9out, r10out, r11out, r12out, r13out, r14out, r15out, HIout,  LOout, Zhighout, Zlowout, PCout, MDRout, In_Portout, Cout;
wire s;

integer i;
//instantiate module for testing
//module encoder (r0out, r1out, r2out, r3out, r4out, r5out, r6out, r7out, r8out, r9out, r10out, r11out, r12out, r13out, r14out, r15out, HIout,  LOout, Zhighout, Zlowout, PCout, MDRout, In_Portout, Cout, S);

encoder encoder_test(.r0out(r0out), .r1out(r1out), .r2out(r2out), .r3out(r3out), .r4out(r4out), .r5out(r5out), .r6out(r6out), .r7out(r7out), .r8out(r8out), .r9out(r9out), .r10out(r10out), .r11out(r11out), .r12out(r12out), .r13out(r13out), .r14out(r14out), .r15out(r15out), .HIout(HIout), .LOout(LOout), .Zhighout(Zhighout), .Zlowout(Zlowout), .PCout(PCout), .MDRout(MDRout), .In_Portout(In_Portout), .Cout(Cout), .S(s))



//init beg block

initial begin
	for (i = 0; i <= 16; i = i+1) begin


		$display ("Testing Rin = %d: Expecting: %d \n Recieved: %d", i, i, s); 
	
	
			
	end

end 
endmodule