neg_new.v.bak

module neg_new (input [31:0] x, output [31:0] y);

reg [31:0] temp;


always @ (*) begin
	for (i = 0; i < 32; i = i+1) begin
		if (x[i] == 1)
			temp[i] = 0;
		else 
			temp[i] = 1;
	end 

	assign y = temp + 1;

end

endmodule