Move __dbg intrinsic to 'arm' (from arm_shared)

Author: Byron

crates/core_arch/src/arm/mod.rs

@@ -79,9 +79,27 @@ pub(crate) mod neon;
 pub use neon::*;
 
 /// Generates the trap instruction `UDF`
-#[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(udf))]
 #[inline]
 pub unsafe fn udf() -> ! {
     crate::intrinsics::abort()
 }
+
+/// Generates a DBG instruction.
+///
+/// This provides a hint to debugging and related systems. The argument must be
+/// a constant integer from 0 to 15 inclusive. See implementation documentation
+/// for the effect (if any) of this instruction and the meaning of the
+/// argument. This is available only when compliling for AArch32.
+// Section 10.1 of ACLE says that the supported arches are: 7, 7-M
+// "The DBG hint instruction is added in ARMv7. It is UNDEFINED in the ARMv6 base architecture, and
+// executes as a NOP instruction in ARMv6K and ARMv6T2." - ARM Architecture Reference Manual ARMv7-A
+// and ARMv7-R edition (ARM DDI 0406C.c) sections D12.4.1 "ARM instruction set support" and D12.4.2
+// "Thumb instruction set support"
+#[cfg(any(target_feature = "v7", doc))]
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+pub unsafe fn __dbg<const IMM4: i32>() {
+    static_assert_imm4!(IMM4);
+    dbg(IMM4);
+}

crates/core_arch/src/arm_shared/hints.rs

@@ -69,27 +69,6 @@ pub unsafe fn __yield() {
     hint(HINT_YIELD);
 }
 
-/// Generates a DBG instruction.
-///
-/// This provides a hint to debugging and related systems. The argument must be
-/// a constant integer from 0 to 15 inclusive. See implementation documentation
-/// for the effect (if any) of this instruction and the meaning of the
-/// argument. This is available only when compliling for AArch32.
-// Section 10.1 of ACLE says that the supported arches are: 7, 7-M
-// "The DBG hint instruction is added in ARMv7. It is UNDEFINED in the ARMv6 base architecture, and
-// executes as a NOP instruction in ARMv6K and ARMv6T2." - ARM Architecture Reference Manual ARMv7-A
-// and ARMv7-R edition (ARM DDI 0406C.c) sections D12.4.1 "ARM instruction set support" and D12.4.2
-// "Thumb instruction set support"
-#[cfg(target_feature = "v7")]
-#[cfg(any(target_arch = "arm", doc))]
-#[doc(cfg(target_arch = "arm"))]
-#[inline(always)]
-#[rustc_legacy_const_generics(0)]
-pub unsafe fn __dbg<const IMM4: i32>() {
-    static_assert_imm4!(IMM4);
-    dbg(IMM4);
-}
-
 /// Generates an unspecified no-op instruction.
 ///
 /// Note that not all architectures provide a distinguished NOP instruction. On

crates/stdarch-verify/tests/arm.rs

@@ -448,6 +448,7 @@ fn verify_all_signatures() {
                 "vpadalq_u8",
                 "vpadalq_u16",
                 "vpadalq_u32",
+                "__dbg",
             ];
             if !skip.contains(&rust.name) {
                 println!(
@@ -479,6 +480,7 @@ fn verify_all_signatures() {
             "vreinterpret_p64_s64",
             "vreinterpret_f32_p64",
             "vreinterpretq_f32_p64",
+            "__dbg",
         ];
         let arm = match map.get(rust.name) {
             Some(i) => i,