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[AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister.
For 0-lane stores, we used to generate code similar to: fmov w8, s0 str w8, [x0, x1, lsl rust-lang#2] instead of: str s0, [x0, x1, lsl rust-lang#2] To correct that: for store lane 0 patterns, directly match to STR <subreg>0. Byte-sized instructions don't have the special case for a 0 index, because FPR8s are defined to have untyped content. rdar://16372710 Differential Revision: http://reviews.llvm.org/D6772 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225181 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1889,6 +1889,33 @@ let Predicates = [IsLE] in {
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}
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} // AddedComplexity = 10
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// Match stores from lane 0 to the appropriate subreg's store.
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multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
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ValueType VecTy, ValueType STy,
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SubRegIndex SubRegIdx,
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Instruction STRW, Instruction STRX> {
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def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
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(ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
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(STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
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GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
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def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
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(ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
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(STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
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GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
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}
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let AddedComplexity = 19 in {
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defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
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defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
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defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
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defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
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defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
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defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
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defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
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}
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//---
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// (unsigned immediate)
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defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",

‎test/CodeGen/AArch64/arm64-st1.ll

Lines changed: 92 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,16 @@ define void @st1lane_16b(<16 x i8> %A, i8* %D) {
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ret void
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}
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define void @st1lane0_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_16b
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; CHECK: umov.b w[[WREG:[0-9]+]], v0[0]
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; CHECK: strb w[[WREG]], [x0, x1]
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%ptr = getelementptr i8* %D, i64 %offset
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%tmp = extractelement <16 x i8> %A, i32 0
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store i8 %tmp, i8* %ptr
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ret void
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}
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define void @st1lane_8h(<8 x i16> %A, i16* %D) {
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; CHECK-LABEL: st1lane_8h
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; CHECK: st1.h
@@ -16,6 +26,15 @@ define void @st1lane_8h(<8 x i16> %A, i16* %D) {
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ret void
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}
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define void @st1lane0_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_8h
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; CHECK: str h0, [x0, x1, lsl #1]
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%ptr = getelementptr i16* %D, i64 %offset
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%tmp = extractelement <8 x i16> %A, i32 0
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store i16 %tmp, i16* %ptr
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ret void
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}
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define void @st1lane_4s(<4 x i32> %A, i32* %D) {
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; CHECK-LABEL: st1lane_4s
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; CHECK: st1.s
@@ -24,6 +43,15 @@ define void @st1lane_4s(<4 x i32> %A, i32* %D) {
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ret void
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}
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define void @st1lane0_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_4s
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; CHECK: str s0, [x0, x1, lsl #2]
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%ptr = getelementptr i32* %D, i64 %offset
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%tmp = extractelement <4 x i32> %A, i32 0
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store i32 %tmp, i32* %ptr
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ret void
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}
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define void @st1lane_4s_float(<4 x float> %A, float* %D) {
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; CHECK-LABEL: st1lane_4s_float
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; CHECK: st1.s
@@ -32,6 +60,15 @@ define void @st1lane_4s_float(<4 x float> %A, float* %D) {
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ret void
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}
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define void @st1lane0_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_4s_float
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; CHECK: str s0, [x0, x1, lsl #2]
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%ptr = getelementptr float* %D, i64 %offset
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%tmp = extractelement <4 x float> %A, i32 0
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store float %tmp, float* %ptr
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ret void
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}
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define void @st1lane_2d(<2 x i64> %A, i64* %D) {
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; CHECK-LABEL: st1lane_2d
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; CHECK: st1.d
@@ -40,6 +77,15 @@ define void @st1lane_2d(<2 x i64> %A, i64* %D) {
4077
ret void
4178
}
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define void @st1lane0_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_2d
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; CHECK: str d0, [x0, x1, lsl #3]
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%ptr = getelementptr i64* %D, i64 %offset
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%tmp = extractelement <2 x i64> %A, i32 0
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store i64 %tmp, i64* %ptr
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ret void
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}
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define void @st1lane_2d_double(<2 x double> %A, double* %D) {
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; CHECK-LABEL: st1lane_2d_double
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; CHECK: st1.d
@@ -48,6 +94,15 @@ define void @st1lane_2d_double(<2 x double> %A, double* %D) {
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ret void
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}
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define void @st1lane0_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_2d_double
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; CHECK: str d0, [x0, x1, lsl #3]
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%ptr = getelementptr double* %D, i64 %offset
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%tmp = extractelement <2 x double> %A, i32 0
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store double %tmp, double* %ptr
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ret void
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}
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define void @st1lane_8b(<8 x i8> %A, i8* %D) {
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; CHECK-LABEL: st1lane_8b
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; CHECK: st1.b
@@ -56,6 +111,16 @@ define void @st1lane_8b(<8 x i8> %A, i8* %D) {
56111
ret void
57112
}
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define void @st1lane0_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_8b
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; CHECK: umov.b w[[WREG:[0-9]+]], v0[0]
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; CHECK: strb w[[WREG]], [x0, x1]
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%ptr = getelementptr i8* %D, i64 %offset
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%tmp = extractelement <8 x i8> %A, i32 0
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store i8 %tmp, i8* %ptr
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ret void
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}
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59124
define void @st1lane_4h(<4 x i16> %A, i16* %D) {
60125
; CHECK-LABEL: st1lane_4h
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; CHECK: st1.h
@@ -64,6 +129,15 @@ define void @st1lane_4h(<4 x i16> %A, i16* %D) {
64129
ret void
65130
}
66131

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define void @st1lane0_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_4h
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; CHECK: str h0, [x0, x1, lsl #1]
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%ptr = getelementptr i16* %D, i64 %offset
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%tmp = extractelement <4 x i16> %A, i32 0
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store i16 %tmp, i16* %ptr
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ret void
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}
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67141
define void @st1lane_2s(<2 x i32> %A, i32* %D) {
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; CHECK-LABEL: st1lane_2s
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; CHECK: st1.s
@@ -72,6 +146,15 @@ define void @st1lane_2s(<2 x i32> %A, i32* %D) {
72146
ret void
73147
}
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define void @st1lane0_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_2s
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; CHECK: str s0, [x0, x1, lsl #2]
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%ptr = getelementptr i32* %D, i64 %offset
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%tmp = extractelement <2 x i32> %A, i32 0
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store i32 %tmp, i32* %ptr
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ret void
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}
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75158
define void @st1lane_2s_float(<2 x float> %A, float* %D) {
76159
; CHECK-LABEL: st1lane_2s_float
77160
; CHECK: st1.s
@@ -80,6 +163,15 @@ define void @st1lane_2s_float(<2 x float> %A, float* %D) {
80163
ret void
81164
}
82165

166+
define void @st1lane0_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_2s_float
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; CHECK: str s0, [x0, x1, lsl #2]
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%ptr = getelementptr float* %D, i64 %offset
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%tmp = extractelement <2 x float> %A, i32 0
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store float %tmp, float* %ptr
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ret void
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}
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83175
define void @st2lane_16b(<16 x i8> %A, <16 x i8> %B, i8* %D) {
84176
; CHECK-LABEL: st2lane_16b
85177
; CHECK: st2.b

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