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David SehrRichard Diamond
David Sehr
authored and
Richard Diamond
committed
Insert denominator zero checks for NaCl
This IR pass for ARM inserts a comparison and a branch to trap if the denominator of a DIV or REM instruction is zero. This makes ARM fault identically to x86 in this case. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2833 [email protected] Review URL: https://codereview.chromium.org/14607004 (cherry picked from commit 8c9803a)
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‎include/llvm/InitializePasses.h

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@@ -278,6 +278,7 @@ void initializeExpandTlsPass(PassRegistry&);
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void initializeExpandVarArgsPass(PassRegistry&);
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void initializeFlattenGlobalsPass(PassRegistry&);
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void initializeGlobalCleanupPass(PassRegistry&);
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void initializeInsertDivideCheckPass(PassRegistry&);
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void initializeNaClCcRewritePass(PassRegistry&);
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void initializePNaClABIVerifyModulePass(PassRegistry&);
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void initializePNaClABIVerifyFunctionsPass(PassRegistry&);

‎include/llvm/Transforms/NaCl.h

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@@ -30,6 +30,7 @@ ModulePass *createFlattenGlobalsPass();
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ModulePass *createGlobalCleanupPass();
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ModulePass *createResolveAliasesPass();
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ModulePass *createStripMetadataPass();
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FunctionPass *createInsertDivideCheckPass();
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Instruction *PhiSafeInsertPt(Use *U);
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void PhiSafeReplaceUses(Use *U, Value *NewVal);

‎lib/Target/ARM/ARMTargetMachine.cpp

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@@ -20,6 +20,9 @@
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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// @LOCALMOD-START
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#include "llvm/Transforms/NaCl.h"
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// @LOCALMOD-END
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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@@ -176,6 +179,9 @@ class ARMPassConfig : public TargetPassConfig {
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virtual bool addPreRegAlloc();
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virtual bool addPreSched2();
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virtual bool addPreEmitPass();
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// @LOCALMOD-START
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virtual void addIRPasses();
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// @LOCALMOD-END
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};
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} // namespace
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@@ -259,6 +265,15 @@ bool ARMPassConfig::addPreEmitPass() {
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return true;
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}
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// @LOCALMOD-START
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void ARMPassConfig::addIRPasses() {
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if (getARMSubtarget().isTargetNaCl()) {
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addPass(createInsertDivideCheckPass());
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}
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TargetPassConfig::addIRPasses();
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}
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// @LOCALMOD-END
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bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for ARM.

‎lib/Transforms/NaCl/CMakeLists.txt

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@@ -7,6 +7,7 @@ add_llvm_library(LLVMNaClTransforms
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ExpandTlsConstantExpr.cpp
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ExpandUtils.cpp
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ExpandVarArgs.cpp
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InsertDivideCheck.cpp
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FlattenGlobals.cpp
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GlobalCleanup.cpp
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StripMetadata.cpp

‎lib/Transforms/NaCl/InsertDivideCheck.cpp

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//===- InsertDivideCheck.cpp - Add divide by zero checks ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass adds a check for divide by zero before every integer DIV or REM.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "add-divide-check"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Transforms/NaCl.h"
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using namespace llvm;
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namespace {
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class InsertDivideCheck : public FunctionPass {
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public:
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static char ID;
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InsertDivideCheck() : FunctionPass(ID) {
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initializeInsertDivideCheckPass(*PassRegistry::getPassRegistry());
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}
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bool runOnFunction(Function &F);
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};
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}
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static BasicBlock *CreateTrapBlock(Function &F, DebugLoc dl) {
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BasicBlock *TrapBlock = BasicBlock::Create(F.getContext(), "divrem.by.zero",
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&F);
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Value *TrapFn = Intrinsic::getDeclaration(F.getParent(), Intrinsic::trap);
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CallInst::Create(TrapFn, "", TrapBlock)->setDebugLoc(dl);
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(new UnreachableInst(F.getContext(), TrapBlock))->setDebugLoc(dl);
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return TrapBlock;
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}
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bool InsertDivideCheck::runOnFunction(Function &F) {
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SmallPtrSet<Instruction*, 8> GuardedDivs;
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// If the pass finds a DIV/REM that needs to be checked for zero denominator,
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// it will insert a new "trap" block, and split the block that contains the
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// DIV/REM into two blocks. The new BasicBlocks are added after the current
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// BasicBlock, so that if there is more than one DIV/REM in the same block,
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// all are visited.
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for (Function::iterator I = F.begin(); I != F.end(); I++) {
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BasicBlock *BB = I;
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for (BasicBlock::iterator BI = BB->begin(), BE = BB->end();
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BI != BE; BI++) {
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BinaryOperator *DivInst = dyn_cast<BinaryOperator>(BI);
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if (!DivInst || (GuardedDivs.count(DivInst) != 0))
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continue;
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unsigned Opcode = DivInst->getOpcode();
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if (Opcode != Instruction::SDiv && Opcode != Instruction::UDiv &&
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Opcode != Instruction::SRem && Opcode != Instruction::URem)
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continue;
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Value *Denominator = DivInst->getOperand(1);
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if (!Denominator->getType()->isIntegerTy())
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continue;
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DebugLoc dl = DivInst->getDebugLoc();
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if (ConstantInt *DenomConst = dyn_cast<ConstantInt>(Denominator)) {
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// Divides by constants do not need a denominator test.
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if (DenomConst->isZero()) {
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// For explicit divides by zero, insert a trap before DIV/REM
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Value *TrapFn = Intrinsic::getDeclaration(F.getParent(),
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Intrinsic::trap);
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CallInst::Create(TrapFn, "", DivInst)->setDebugLoc(dl);
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}
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continue;
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}
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// Create a trap block.
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BasicBlock *TrapBlock = CreateTrapBlock(F, dl);
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// Move instructions in BB from DivInst to BB's end to a new block.
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BasicBlock *Successor = BB->splitBasicBlock(BI, "guarded.divrem");
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// Remove the unconditional branch inserted by splitBasicBlock.
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BB->getTerminator()->eraseFromParent();
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// Remember that DivInst was already processed, so that when we process
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// inserted blocks later, we do not attempt to again guard it.
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GuardedDivs.insert(DivInst);
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// Compare the denominator with zero.
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Value *Zero = ConstantInt::get(Denominator->getType(), 0);
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Value *DenomIsZero = new ICmpInst(*BB, ICmpInst::ICMP_EQ, Denominator,
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Zero, "");
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// Put in a condbranch to the trap block.
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BranchInst::Create(TrapBlock, Successor, DenomIsZero, BB);
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// BI is invalidated when we split. Stop the BasicBlock iterator.
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break;
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}
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}
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return false;
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}
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char InsertDivideCheck::ID = 0;
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INITIALIZE_PASS(InsertDivideCheck, "insert-divide-check",
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"Insert divide by zero checks", false, false)
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FunctionPass *llvm::createInsertDivideCheckPass() {
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return new InsertDivideCheck();
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}

‎test/NaCl/ARM/divrem-guards-complex.ll

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; RUN: opt < %s -insert-divide-check -S | FileCheck -check-prefix=OPT %s
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declare void @foo()
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; Check for multiple divs that occur one block.
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define i32 @twodivs_one_block(i32 %x, i32 %y) #0 {
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entry:
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call void @foo()
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br label %divblock
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divblock:
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%div1 = sdiv i32 %x, %y
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%div2 = sdiv i32 %x, %y
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; OPT: %0 = icmp eq i32 %y, 0
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; OPT-NEXT: br i1 %0, label %divrem.by.zero, label %guarded.divrem
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; OPT: guarded.divrem:
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; OPT-NEXT: sdiv
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; OPT: %1 = icmp eq i32 %y, 0
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; OPT-NEXT: br i1 %1, label %divrem.by.zero1, label %guarded.divrem2
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; OPT: guarded.divrem2:
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; OPT-NEXT: sdiv
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; OPT-NEXT: add
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; OPT: divrem.by.zero:
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; OPT-NEXT: call void @llvm.trap()
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; OPT-NEXT: unreachable
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; OPT: divrem.by.zero1:
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; OPT-NEXT: call void @llvm.trap()
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; OPT-NEXT: unreachable
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%sum = add i32 %div1, %div2
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ret i32 %sum
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}
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define i32 @twodivs_three_blocks(i32 %x, i32 %y) #0 {
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entry:
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call void @foo()
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br label %divblock
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divblock:
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%div1 = sdiv i32 %x, %y
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; OPT: %0 = icmp eq i32 %y, 0
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; OPT-NEXT: br i1 %0, label %divrem.by.zero, label %guarded.divrem
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; OPT: guarded.divrem:
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; OPT-NEXT: sdiv
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; OPT-NEXT: br label %exitblock
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br label %exitblock
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exitblock:
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call void @foo()
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%div2 = sdiv i32 %x, %y
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; OPT: %1 = icmp eq i32 %y, 0
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; OPT-NEXT: br i1 %1, label %divrem.by.zero1, label %guarded.divrem2
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; OPT: guarded.divrem2:
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; OPT-NEXT: sdiv
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; OPT-NEXT: add
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; OPT: divrem.by.zero:
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; OPT-NEXT: call void @llvm.trap()
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; OPT-NEXT: unreachable
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; OPT: divrem.by.zero1:
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; OPT-NEXT: call void @llvm.trap()
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; OPT-NEXT: unreachable
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%sum = add i32 %div1, %div2
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ret i32 %sum
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}
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; Check for divs that occur in blocks with multiple predecessors.
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define i32 @onediv_two_predecessors(i32 %x, i32 %y) #0 {
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entry:
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call void @foo()
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br label %divblock
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divblock:
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%x1 = phi i32 [%x, %entry], [%x2, %divblock]
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%div1 = sdiv i32 %x, %y
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; OPT: %0 = icmp eq i32 %y, 0
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; OPT-NEXT: br i1 %0, label %divrem.by.zero, label %guarded.divrem
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; OPT: guarded.divrem:
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; OPT-NEXT: sdiv
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; OPT-NEXT: sub
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; OPT: divrem.by.zero:
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; OPT-NEXT: call void @llvm.trap()
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; OPT-NEXT: unreachable
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%x2 = sub i32 %x1, 1
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%p = icmp ne i32 %x2, 0
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br i1 %p, label %divblock, label %exitblock
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exitblock:
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call void @foo()
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ret i32 %div1
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}
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‎test/NaCl/ARM/divrem-guards.ll

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; RUN: opt < %s -insert-divide-check -S | FileCheck -check-prefix=OPT %s
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; RUN: llc -mtriple=armv7-unknown-nacl -sfi-branch -filetype=obj %s -o - \
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; RUN: | llvm-objdump -disassemble -triple armv7 -mattr=+nacl-trap - \
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; RUN: | FileCheck -check-prefix=ARM %s
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; Check for all four operators that need guards.
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define i32 @mysdiv(i32 %x, i32 %y) #0 {
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entry:
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%div1 = sdiv i32 %x, %y
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; OPT: %0 = icmp eq i32 %y, 0
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; OPT-NEXT: br i1 %0, label %divrem.by.zero, label %guarded.divrem
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; OPT: guarded.divrem:
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; OPT-NEXT: sdiv
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; OPT-NEXT: ret
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; OPT: divrem.by.zero:
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; OPT-NEXT: call void @llvm.trap()
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; OPT-NEXT: unreachable
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; ARM: cmp r1, #0
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; ARM-NEXT: beq
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ret i32 %div1
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; ARM: f0 de fe e7
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}
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define i32 @myudiv(i32 %x, i32 %y) #0 {
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entry:
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%div1 = udiv i32 %x, %y
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; OPT: %0 = icmp eq i32 %y, 0
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; OPT-NEXT: br i1 %0, label %divrem.by.zero, label %guarded.divrem
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; OPT: guarded.divrem:
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; OPT-NEXT: udiv
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; OPT-NEXT: ret
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; OPT: divrem.by.zero:
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; OPT-NEXT: call void @llvm.trap()
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; OPT-NEXT: unreachable
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; ARM: cmp r1, #0
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; ARM-NEXT: beq
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ret i32 %div1
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; ARM: f0 de fe e7
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}
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define i32 @mysrem(i32 %x, i32 %y) #0 {
43+
entry:
44+
%rem1 = srem i32 %x, %y
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; OPT: %0 = icmp eq i32 %y, 0
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; OPT-NEXT: br i1 %0, label %divrem.by.zero, label %guarded.divrem
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; OPT: guarded.divrem:
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; OPT-NEXT: srem
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; OPT-NEXT: ret
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; OPT: divrem.by.zero:
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; OPT-NEXT: call void @llvm.trap()
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; OPT-NEXT: unreachable
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; ARM: cmp r1, #0
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; ARM-NEXT: beq
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ret i32 %rem1
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; ARM: f0 de fe e7
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}
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define i32 @myurem(i32 %x, i32 %y) #0 {
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entry:
61+
%rem1 = urem i32 %x, %y
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; OPT: %0 = icmp eq i32 %y, 0
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; OPT-NEXT: br i1 %0, label %divrem.by.zero, label %guarded.divrem
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; OPT: guarded.divrem:
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; OPT-NEXT: urem
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; OPT-NEXT: ret
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; OPT: divrem.by.zero:
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; OPT-NEXT: call void @llvm.trap()
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; OPT-NEXT: unreachable
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; ARM: cmp r1, #0
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; ARM-NEXT: beq
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ret i32 %rem1
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; ARM: f0 de fe e7
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}
75+
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; Divides by non-zero constants should not be guarded.
77+
define i32 @mysdiv_const(i32 %x) #0 {
78+
entry:
79+
%div1 = sdiv i32 %x, 10
80+
; OPT-NOT: icmp
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; OPT-NOT: br
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; OPT-NOT: guarded.divrem:
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; OPT-NOT: divrem.by.zero:
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; OPT-NOT: call void @llvm.trap()
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; OPT-NOT: unreachable
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; ARM-NOT: cmp r1, #0
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; ARM-NOT: f0 de fe e7
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ret i32 %div1
89+
}
90+
91+
; Divides by explicit zero should prefixed by a trap.
92+
define i32 @mysdiv_zero(i32 %x) #0 {
93+
entry:
94+
%div1 = sdiv i32 %x, 0
95+
; OPT-NOT: guarded.divrem:
96+
; OPT-NOT: divrem.by.zero:
97+
; OPT: call void @llvm.trap()
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; OPT-NEXT: sdiv
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; ARM-NOT: cmp r1, #0
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; ARM: f0 de fe e7
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ret i32 %div1
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}
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attributes #0 = { nounwind }

‎tools/opt/opt.cpp

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@@ -431,6 +431,7 @@ int main(int argc, char **argv) {
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initializeExpandVarArgsPass(Registry);
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initializeFlattenGlobalsPass(Registry);
433433
initializeGlobalCleanupPass(Registry);
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initializeInsertDivideCheckPass(Registry);
434435
initializePNaClABIVerifyFunctionsPass(Registry);
435436
initializePNaClABIVerifyModulePass(Registry);
436437
initializeResolveAliasesPass(Registry);

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