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XinWang10XinWang10
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[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction (llvm#75582)
R16-R31 was added into GPRs in llvm#70958, This patch supports the encoding/decoding for promoted SHA instruction in EVEX space. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
1 parent c4457e1 commit 037c220

26 files changed

+290
-32
lines changed

‎llvm/lib/Target/X86/X86InstrAsmAlias.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -686,3 +686,11 @@ def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
686686
def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>;
687687
def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;
688688

689+
// Aliases with explicit %xmm0
690+
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
691+
(SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
692+
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
693+
(SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
694+
695+
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
696+
(SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>;

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 65 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -6706,31 +6706,31 @@ let Constraints = "$src1 = $dst" in {
67066706

67076707
// FIXME: Is there a better scheduler class for SHA than WriteVecIMul?
67086708
multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
6709-
X86FoldableSchedWrite sched, bit UsesXMM0 = 0> {
6710-
def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
6711-
(ins VR128:$src1, VR128:$src2),
6712-
!if(UsesXMM0,
6713-
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
6714-
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
6715-
[!if(UsesXMM0,
6716-
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
6717-
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
6718-
T8PS, Sched<[sched]>;
6719-
6720-
def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
6721-
(ins VR128:$src1, i128mem:$src2),
6722-
!if(UsesXMM0,
6723-
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
6724-
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
6725-
[!if(UsesXMM0,
6726-
(set VR128:$dst, (IntId VR128:$src1,
6727-
(memop addr:$src2), XMM0)),
6728-
(set VR128:$dst, (IntId VR128:$src1,
6729-
(memop addr:$src2))))]>, T8PS,
6730-
Sched<[sched.Folded, sched.ReadAfterFold]>;
6709+
X86FoldableSchedWrite sched, string Suffix = "", bit UsesXMM0 = 0> {
6710+
def rr#Suffix : I<Opc, MRMSrcReg, (outs VR128:$dst),
6711+
(ins VR128:$src1, VR128:$src2),
6712+
!if(UsesXMM0,
6713+
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
6714+
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
6715+
[!if(UsesXMM0,
6716+
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
6717+
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
6718+
T8PS, Sched<[sched]>;
6719+
6720+
def rm#Suffix : I<Opc, MRMSrcMem, (outs VR128:$dst),
6721+
(ins VR128:$src1, i128mem:$src2),
6722+
!if(UsesXMM0,
6723+
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
6724+
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
6725+
[!if(UsesXMM0,
6726+
(set VR128:$dst, (IntId VR128:$src1,
6727+
(memop addr:$src2), XMM0)),
6728+
(set VR128:$dst, (IntId VR128:$src1,
6729+
(memop addr:$src2))))]>, T8PS,
6730+
Sched<[sched.Folded, sched.ReadAfterFold]>;
67316731
}
67326732

6733-
let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
6733+
let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
67346734
def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
67356735
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
67366736
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
@@ -6757,19 +6757,55 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
67576757

67586758
let Uses=[XMM0] in
67596759
defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2,
6760-
SchedWriteVecIMul.XMM, 1>;
6760+
SchedWriteVecIMul.XMM, "", 1>;
67616761

67626762
defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1,
67636763
SchedWriteVecIMul.XMM>;
67646764
defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2,
67656765
SchedWriteVecIMul.XMM>;
67666766
}
67676767

6768-
// Aliases with explicit %xmm0
6769-
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
6770-
(SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
6771-
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
6772-
(SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
6768+
let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode] in {
6769+
def SHA1RNDS4rri_EVEX: Ii8<0xD4, MRMSrcReg, (outs VR128:$dst),
6770+
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
6771+
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6772+
[(set VR128:$dst,
6773+
(int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
6774+
(i8 timm:$src3)))]>,
6775+
EVEX_NoCD8, T_MAP4PS, Sched<[SchedWriteVecIMul.XMM]>;
6776+
def SHA1RNDS4rmi_EVEX: Ii8<0xD4, MRMSrcMem, (outs VR128:$dst),
6777+
(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
6778+
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6779+
[(set VR128:$dst,
6780+
(int_x86_sha1rnds4 VR128:$src1,
6781+
(memop addr:$src2),
6782+
(i8 timm:$src3)))]>,
6783+
EVEX_NoCD8, T_MAP4PS,
6784+
Sched<[SchedWriteVecIMul.XMM.Folded,
6785+
SchedWriteVecIMul.XMM.ReadAfterFold]>;
6786+
6787+
defm SHA1NEXTE : SHAI_binop<0xD8, "sha1nexte", int_x86_sha1nexte,
6788+
SchedWriteVecIMul.XMM, "_EVEX">,
6789+
EVEX_NoCD8, T_MAP4PS;
6790+
defm SHA1MSG1 : SHAI_binop<0xD9, "sha1msg1", int_x86_sha1msg1,
6791+
SchedWriteVecIMul.XMM, "_EVEX">,
6792+
EVEX_NoCD8, T_MAP4PS;
6793+
defm SHA1MSG2 : SHAI_binop<0xDA, "sha1msg2", int_x86_sha1msg2,
6794+
SchedWriteVecIMul.XMM, "_EVEX">,
6795+
EVEX_NoCD8, T_MAP4PS;
6796+
6797+
let Uses=[XMM0] in
6798+
defm SHA256RNDS2 : SHAI_binop<0xDB, "sha256rnds2", int_x86_sha256rnds2,
6799+
SchedWriteVecIMul.XMM, "_EVEX", 1>,
6800+
EVEX_NoCD8, T_MAP4PS;
6801+
6802+
defm SHA256MSG1 : SHAI_binop<0xDC, "sha256msg1", int_x86_sha256msg1,
6803+
SchedWriteVecIMul.XMM, "_EVEX">,
6804+
EVEX_NoCD8, T_MAP4PS;
6805+
defm SHA256MSG2 : SHAI_binop<0xDD, "sha256msg2", int_x86_sha256msg2,
6806+
SchedWriteVecIMul.XMM, "_EVEX">,
6807+
EVEX_NoCD8, T_MAP4PS;
6808+
}
67736809

67746810
//===----------------------------------------------------------------------===//
67756811
// AES-NI Instructions

‎llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt

Lines changed: 10 additions & 0 deletions
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@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: sha1msg1 %xmm13, %xmm12
5+
# INTEL: sha1msg1 xmm12, xmm13
6+
0x45,0x0f,0x38,0xc9,0xe5
7+
8+
# ATT: sha1msg1 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
10+
0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt

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@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: sha1msg2 %xmm13, %xmm12
5+
# INTEL: sha1msg2 xmm12, xmm13
6+
0x45,0x0f,0x38,0xca,0xe5
7+
8+
# ATT: sha1msg2 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
10+
0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt

Lines changed: 10 additions & 0 deletions
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@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: sha1nexte %xmm13, %xmm12
5+
# INTEL: sha1nexte xmm12, xmm13
6+
0x45,0x0f,0x38,0xc8,0xe5
7+
8+
# ATT: sha1nexte 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
10+
0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: sha1rnds4 $123, %xmm13, %xmm12
5+
# INTEL: sha1rnds4 xmm12, xmm13, 123
6+
0x45,0x0f,0x3a,0xcc,0xe5,0x7b
7+
8+
# ATT: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
10+
0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b

‎llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: sha256msg1 %xmm13, %xmm12
5+
# INTEL: sha256msg1 xmm12, xmm13
6+
0x45,0x0f,0x38,0xcc,0xe5
7+
8+
# ATT: sha256msg1 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
10+
0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt

Lines changed: 10 additions & 0 deletions
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@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: sha256msg2 %xmm13, %xmm12
5+
# INTEL: sha256msg2 xmm12, xmm13
6+
0x45,0x0f,0x38,0xcd,0xe5
7+
8+
# ATT: sha256msg2 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
10+
0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: sha256rnds2 %xmm0, %xmm13, %xmm12
5+
# INTEL: sha256rnds2 xmm12, xmm13, xmm0
6+
0x45,0x0f,0x38,0xcb,0xe5
7+
8+
# ATT: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
10+
0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/X86/apx/sha1msg1-att.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sha1msg1 %xmm13, %xmm12
4+
# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
5+
sha1msg1 %xmm13, %xmm12
6+
7+
# CHECK: sha1msg1 291(%r28,%r29,4), %xmm12
8+
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
9+
sha1msg1 291(%r28,%r29,4), %xmm12

‎llvm/test/MC/X86/apx/sha1msg1-intel.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sha1msg1 xmm12, xmm13
4+
# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
5+
sha1msg1 xmm12, xmm13
6+
7+
# CHECK: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
8+
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
9+
sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/sha1msg2-att.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sha1msg2 %xmm13, %xmm12
4+
# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
5+
sha1msg2 %xmm13, %xmm12
6+
7+
# CHECK: sha1msg2 291(%r28,%r29,4), %xmm12
8+
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
9+
sha1msg2 291(%r28,%r29,4), %xmm12

‎llvm/test/MC/X86/apx/sha1msg2-intel.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sha1msg2 xmm12, xmm13
4+
# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
5+
sha1msg2 xmm12, xmm13
6+
7+
# CHECK: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
8+
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
9+
sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/sha1nexte-att.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sha1nexte %xmm13, %xmm12
4+
# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
5+
sha1nexte %xmm13, %xmm12
6+
7+
# CHECK: sha1nexte 291(%r28,%r29,4), %xmm12
8+
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
9+
sha1nexte 291(%r28,%r29,4), %xmm12

‎llvm/test/MC/X86/apx/sha1nexte-intel.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sha1nexte xmm12, xmm13
4+
# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
5+
sha1nexte xmm12, xmm13
6+
7+
# CHECK: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
8+
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
9+
sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/sha1rnds4-att.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sha1rnds4 $123, %xmm13, %xmm12
4+
# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
5+
sha1rnds4 $123, %xmm13, %xmm12
6+
7+
# CHECK: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
8+
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
9+
sha1rnds4 $123, 291(%r28,%r29,4), %xmm12

‎llvm/test/MC/X86/apx/sha1rnds4-intel.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sha1rnds4 xmm12, xmm13, 123
4+
# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
5+
sha1rnds4 xmm12, xmm13, 123
6+
7+
# CHECK: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
8+
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
9+
sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123

‎llvm/test/MC/X86/apx/sha256msg1-att.s

Lines changed: 9 additions & 0 deletions
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
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# CHECK: sha256msg1 %xmm13, %xmm12
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# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
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sha256msg1 %xmm13, %xmm12
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# CHECK: sha256msg1 291(%r28,%r29,4), %xmm12
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# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
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sha256msg1 291(%r28,%r29,4), %xmm12

‎llvm/test/MC/X86/apx/sha256msg1-intel.s

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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
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# CHECK: sha256msg1 xmm12, xmm13
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# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
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sha256msg1 xmm12, xmm13
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# CHECK: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
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# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
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sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/sha256msg2-att.s

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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
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# CHECK: sha256msg2 %xmm13, %xmm12
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# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
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sha256msg2 %xmm13, %xmm12
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# CHECK: sha256msg2 291(%r28,%r29,4), %xmm12
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# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
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sha256msg2 291(%r28,%r29,4), %xmm12

‎llvm/test/MC/X86/apx/sha256msg2-intel.s

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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
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# CHECK: sha256msg2 xmm12, xmm13
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# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
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sha256msg2 xmm12, xmm13
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# CHECK: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
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# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
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sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/sha256rnds2-att.s

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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
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# CHECK: sha256rnds2 %xmm0, %xmm13, %xmm12
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# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5]
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sha256rnds2 %xmm0, %xmm13, %xmm12
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# CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
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# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
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sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
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# CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
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# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
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sha256rnds2 291(%r28,%r29,4), %xmm12

‎llvm/test/MC/X86/apx/sha256rnds2-intel.s

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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
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# CHECK: sha256rnds2 xmm12, xmm13, xmm0
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# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5]
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sha256rnds2 xmm12, xmm13, xmm0
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# CHECK: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
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# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
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sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
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# CHECK: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
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# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
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sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/x86_64-asm-match.s

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// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
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// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
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// CHECK: Opcode result: complete match, selecting this opcode
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// CHECK: AsmMatcher: found 2 encodings with mnemonic 'sha1rnds4'
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// CHECK: AsmMatcher: found 4 encodings with mnemonic 'sha1rnds4'
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// CHECK: Trying to match opcode SHA1RNDS4rri
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// CHECK: Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:1): match success using generic matcher
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// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher

‎llvm/test/TableGen/x86-fold-tables.inc

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@@ -1632,12 +1632,19 @@ static const X86FoldTableEntry Table2[] = {
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{X86::SBB64rr, X86::SBB64rm, 0},
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{X86::SBB8rr, X86::SBB8rm, 0},
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{X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16},
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{X86::SHA1MSG1rr_EVEX, X86::SHA1MSG1rm_EVEX, TB_ALIGN_16},
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{X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16},
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{X86::SHA1MSG2rr_EVEX, X86::SHA1MSG2rm_EVEX, TB_ALIGN_16},
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{X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16},
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{X86::SHA1NEXTErr_EVEX, X86::SHA1NEXTErm_EVEX, TB_ALIGN_16},
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{X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16},
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{X86::SHA1RNDS4rri_EVEX, X86::SHA1RNDS4rmi_EVEX, TB_ALIGN_16},
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{X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16},
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{X86::SHA256MSG1rr_EVEX, X86::SHA256MSG1rm_EVEX, TB_ALIGN_16},
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{X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16},
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{X86::SHA256MSG2rr_EVEX, X86::SHA256MSG2rm_EVEX, TB_ALIGN_16},
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{X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16},
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{X86::SHA256RNDS2rr_EVEX, X86::SHA256RNDS2rm_EVEX, TB_ALIGN_16},
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{X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16},
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{X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16},
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{X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE},

‎llvm/utils/TableGen/X86FoldTablesEmitter.cpp

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@@ -32,8 +32,10 @@ struct ManualMapEntry {
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};
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// List of instructions requiring explicitly aligned memory.
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const char *ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS",
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"MOVNTPD", "MOVNTDQ", "MOVNTDQA"};
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const char *ExplicitAlign[] = {
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"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", "MOVNTPD",
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"MOVNTDQ", "MOVNTDQA", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE",
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"SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2"};
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// List of instructions NOT requiring explicit memory alignment.
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const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD",

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