Merged main:be5ecc35efc902a4742669d41a88cfd88babb245 into amd-gfx:fee3baa081ca

Local branch amd-gfx fee3baa Merged main:99b85cae628c1cc5641944290712cd84ccf1f6c8 into amd-gfx:f09ee8740921
Remote branch main be5ecc3 [RISCV] Dont move source if passthru already dominates in vmv.v.v peephole (llvm#105792)

Author: SC llvm team

llvm/cmake/config-ix.cmake

@@ -260,7 +260,7 @@ if(C_SUPPORTS_WERROR_UNGUARDED_AVAILABILITY_NEW)
 endif()
 
 check_cxx_symbol_exists(logf128 cmath HAS_LOGF128)
-check_symbol_exists(__powerpc64le__ "" __PPC64LE)
+check_symbol_exists(__powerpc__ "" __PPC64LE)
 if(HAS_LOGF128 AND NOT __PPC64LE)
     set(LLVM_HAS_LOGF128 On)
     add_compile_definitions(HAS_LOGF128)

llvm/include/llvm/Config/llvm-config.h.cmake

@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 509529
+#define LLVM_MAIN_REVISION 509532
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP

llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp

@@ -437,6 +437,22 @@ static bool isSafeToMove(const MachineInstr &From, const MachineInstr &To) {
   return From.isSafeToMove(SawStore);
 }
 
+/// Given A and B are in the same MBB, returns true if A comes before B.
+static bool dominates(MachineBasicBlock::const_iterator A,
+                      MachineBasicBlock::const_iterator B) {
+  assert(A->getParent() == B->getParent());
+  const MachineBasicBlock *MBB = A->getParent();
+  auto MBBEnd = MBB->end();
+  if (B == MBBEnd)
+    return true;
+
+  MachineBasicBlock::const_iterator I = MBB->begin();
+  for (; &*I != A && &*I != B; ++I)
+    ;
+
+  return &*I == A;
+}
+
 /// If a PseudoVMV_V_V is the only user of its input, fold its passthru and VL
 /// into it.
 ///
@@ -481,12 +497,15 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
   if (!isVLKnownLE(SrcVL, MI.getOperand(3)))
     return false;
 
-  // If Src ends up using MI's passthru/VL, move it so it can access it.
-  // TODO: We don't need to do this if they already dominate Src.
-  if (!SrcPassthru.isIdenticalTo(Passthru)) {
-    if (!isSafeToMove(*Src, MI))
-      return false;
-    Src->moveBefore(&MI);
+  // If the new passthru doesn't dominate Src, try to move Src so it does.
+  if (Passthru.getReg() != RISCV::NoRegister) {
+    MachineInstr *PassthruDef = MRI->getVRegDef(Passthru.getReg());
+    if (PassthruDef->getParent() == Src->getParent() &&
+        !dominates(PassthruDef, Src)) {
+      if (!isSafeToMove(*Src, *PassthruDef->getNextNode()))
+        return false;
+      Src->moveBefore(PassthruDef->getNextNode());
+    }
   }
 
   if (SrcPassthru.getReg() != Passthru.getReg()) {

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

@@ -4201,5 +4201,24 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
     }
   }
 
+  // select (trunc nuw X to i1), X, Y --> select (trunc nuw X to i1), 1, Y
+  // select (trunc nuw X to i1), Y, X --> select (trunc nuw X to i1), Y, 0
+  // select (trunc nsw X to i1), X, Y --> select (trunc nsw X to i1), -1, Y
+  // select (trunc nsw X to i1), Y, X --> select (trunc nsw X to i1), Y, 0
+  Value *Trunc;
+  if (match(CondVal, m_NUWTrunc(m_Value(Trunc)))) {
+    if (TrueVal == Trunc)
+      return replaceOperand(SI, 1, ConstantInt::get(TrueVal->getType(), 1));
+    if (FalseVal == Trunc)
+      return replaceOperand(SI, 2, ConstantInt::get(FalseVal->getType(), 0));
+  }
+  if (match(CondVal, m_NSWTrunc(m_Value(Trunc)))) {
+    if (TrueVal == Trunc)
+      return replaceOperand(SI, 1,
+                            Constant::getAllOnesValue(TrueVal->getType()));
+    if (FalseVal == Trunc)
+      return replaceOperand(SI, 2, ConstantInt::get(FalseVal->getType(), 0));
+  }
+
   return nullptr;
 }

llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir

@@ -0,0 +1,20 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
+# RUN:     -verify-machineinstrs | FileCheck %s
+
+---
+name: move_src
+body: |
+  bb.0:
+    liveins: $v8
+    ; CHECK-LABEL: name: move_src
+    ; CHECK: liveins: $v8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %passthru:vr = COPY $v8
+    ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
+    %passthru:vr = COPY $v8
+    %y:gpr = ADDI $x0, 1
+    %z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */
+...

llvm/test/Transforms/InstCombine/fold-select-trunc.ll

@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i8 @fold_select_trunc_nuw_true(i8 %x, i8 %y) {
+; CHECK-LABEL: @fold_select_trunc_nuw_true(
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc nuw i8 [[X:%.*]] to i1
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[TRUNC]], i8 1, i8 [[Y:%.*]]
+; CHECK-NEXT:    ret i8 [[RET]]
+;
+  %trunc = trunc nuw i8 %x to i1
+  %ret = select i1 %trunc, i8 %x, i8 %y
+  ret i8 %ret
+}
+
+define i8 @fold_select_trunc_nuw_false(i8 %x, i8 %y) {
+; CHECK-LABEL: @fold_select_trunc_nuw_false(
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc nuw i8 [[X:%.*]] to i1
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[TRUNC]], i8 [[Y:%.*]], i8 0
+; CHECK-NEXT:    ret i8 [[RET]]
+;
+  %trunc = trunc nuw i8 %x to i1
+  %ret = select i1 %trunc, i8 %y, i8 %x
+  ret i8 %ret
+}
+
+define i128 @fold_select_trunc_nsw_true(i128 %x, i128 %y) {
+; CHECK-LABEL: @fold_select_trunc_nsw_true(
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc nsw i128 [[X:%.*]] to i1
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[TRUNC]], i128 -1, i128 [[Y:%.*]]
+; CHECK-NEXT:    ret i128 [[RET]]
+;
+  %trunc = trunc nsw i128 %x to i1
+  %ret = select i1 %trunc, i128 %x, i128 %y
+  ret i128 %ret
+}
+
+define i8 @fold_select_trunc_nsw_false(i8 %x, i8 %y) {
+; CHECK-LABEL: @fold_select_trunc_nsw_false(
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc nsw i8 [[X:%.*]] to i1
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[TRUNC]], i8 [[Y:%.*]], i8 0
+; CHECK-NEXT:    ret i8 [[RET]]
+;
+  %trunc = trunc nsw i8 %x to i1
+  %ret = select i1 %trunc, i8 %y, i8 %x
+  ret i8 %ret
+}
+
+define i8 @fold_select_trunc_negative(i8 %x, i8 %y) {
+; CHECK-LABEL: @fold_select_trunc_negative(
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i8 [[X:%.*]] to i1
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[TRUNC]], i8 [[X]], i8 [[Y:%.*]]
+; CHECK-NEXT:    ret i8 [[RET]]
+;
+  %trunc = trunc i8 %x to i1
+  %ret = select i1 %trunc, i8 %x, i8 %y
+  ret i8 %ret
+}
+
+define <2 x i8> @fold_select_trunc_vector(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @fold_select_trunc_vector(
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc nuw <2 x i8> [[X:%.*]] to <2 x i1>
+; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[TRUNC]], <2 x i8> <i8 1, i8 1>, <2 x i8> [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i8> [[RET]]
+;
+  %trunc = trunc nuw <2 x i8> %x to <2 x i1>
+  %ret = select <2 x i1> %trunc, <2 x i8> %x, <2 x i8> %y
+  ret <2 x i8> %ret
+}