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[AArch64] NFC : Change the way SVE pseudos are appended
 * SVE pseudos don't pick up the right latency information during MI scheduling as the regex do not match with instruction name. * Move UNDEF, PSEUDO, and ZERO to the end of actual SVE instruction * Some CPUs *td files will be fixed in the next commit Differential Revision: https://reviews.llvm.org/D154232
1 parent 112d769 commit c35d207

7 files changed

+227
-227
lines changed

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2368,12 +2368,12 @@ let Predicates = [HasSVEorSME] in {
23682368
defm : ld1rq_pat<nxv4i32, AArch64ld1rq_z, LD1RQ_W, am_sve_regreg_lsl2>;
23692369
defm : ld1rq_pat<nxv2i64, AArch64ld1rq_z, LD1RQ_D, am_sve_regreg_lsl3>;
23702370

2371-
def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (SXTW_ZPmZ_UNDEF_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
2372-
def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (SXTH_ZPmZ_UNDEF_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
2373-
def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i8), (SXTB_ZPmZ_UNDEF_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
2374-
def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (SXTH_ZPmZ_UNDEF_S (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>;
2375-
def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i8), (SXTB_ZPmZ_UNDEF_S (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>;
2376-
def : Pat<(sext_inreg (nxv8i16 ZPR:$Zs), nxv8i8), (SXTB_ZPmZ_UNDEF_H (IMPLICIT_DEF), (PTRUE_H 31), ZPR:$Zs)>;
2371+
def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (SXTW_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
2372+
def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (SXTH_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
2373+
def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i8), (SXTB_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
2374+
def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (SXTH_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>;
2375+
def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i8), (SXTB_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>;
2376+
def : Pat<(sext_inreg (nxv8i16 ZPR:$Zs), nxv8i8), (SXTB_ZPmZ_H_UNDEF (IMPLICIT_DEF), (PTRUE_H 31), ZPR:$Zs)>;
23772377

23782378
// General case that we ideally never want to match.
23792379
def : Pat<(vscale GPR64:$scale), (MADDXrrr (UBFMXri (RDVLI_XI 1), 4, 63), $scale, XZR)>;

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -2065,7 +2065,7 @@ def : InstRW<[V2Write_2cyc_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]$")>;
20652065

20662066
// Arithmetic, absolute diff
20672067
def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]$",
2068-
"^[SU]ABD_ZPZZ_UNDEF_[BHSD]$")>;
2068+
"^[SU]ABD_ZPZZ_[BHSD]_UNDEF$")>;
20692069

20702070
// Arithmetic, absolute diff accum
20712071
def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>;
@@ -2079,7 +2079,7 @@ def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]$")>;
20792079
// Arithmetic, basic
20802080
def : InstRW<[V2Write_2cyc_1V],
20812081
(instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]$",
2082-
"^(ABS|CNOT|NEG)_ZPmZ_UNDEF_[BHSD]$",
2082+
"^(ABS|CNOT|NEG)_ZPmZ_[BHSD]_UNDEF$",
20832083
"^(ADD|SUB)_ZZZ_[BHSD]$",
20842084
"^(ADD|SUB|SUBR)_ZI_[BHSD]$",
20852085
"^ADR_[SU]XTW_ZZZ_D_[0123]$",
@@ -2093,7 +2093,7 @@ def : InstRW<[V2Write_2cyc_1V],
20932093
def : InstRW<[V2Write_2cyc_1V],
20942094
(instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]$",
20952095
"^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]$",
2096-
"^SQ(ABS|NEG)_ZPmZ_UNDEF_[BHSD]$",
2096+
"^SQ(ABS|NEG)_ZPmZ_[BHSD]_UNDEF$",
20972097
"^[SU]Q(ADD|SUB)_ZZZ_[BHSD]$",
20982098
"^[SU]Q(ADD|SUB)_ZI_[BHSD]$",
20992099
"^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]$",
@@ -2116,7 +2116,7 @@ def : InstRW<[V2Write_2cyc_1V13],
21162116
"^(ASR|LSL|LSR)_ZPmI_[BHSD]$",
21172117
"^(ASR|LSL|LSR)_ZPmZ_[BHSD]$",
21182118
"^(ASR|LSL|LSR)_ZZI_[BHSD]$",
2119-
"^(ASR|LSL|LSR)_ZPZ[IZ]_UNDEF_[BHSD]$",
2119+
"^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]_UNDEF$",
21202120
"^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]$")>;
21212121

21222122
// Arithmetic, shift and accumulate
@@ -2133,7 +2133,7 @@ def : InstRW<[V2Write_2cyc_1V13], (instregex "^(SLI|SRI)_ZZI_[BHSD]$")>;
21332133
def : InstRW<[V2Write_4cyc_1V13],
21342134
(instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]$",
21352135
"^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]$",
2136-
"^[SU]QR?SHL_ZPZZ_UNDEF_[BHSD]$",
2136+
"^[SU]QR?SHL_ZPZZ_[BHSD]_UNDEF$",
21372137
"^(SQSHL|SQSHLU|UQSHL)_ZPmI_[BHSD]$",
21382138
"^SQSHRU?N[BT]_ZZI_[BHS]$",
21392139
"^UQR?SHRN[BT]_ZZI_[BHS]$")>;
@@ -2143,7 +2143,7 @@ def : InstRW<[V2Write_4cyc_1V13], (instregex "^ASRD_ZPmI_[BHSD]$")>;
21432143

21442144
// Arithmetic, shift rounding
21452145
def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]$",
2146-
"^[SU]RSHL_ZPZZ_UNDEF_[BHSD]$",
2146+
"^[SU]RSHL_ZPZZ_[BHSD]_UNDEF$",
21472147
"^[SU]RSHR_ZPmI_[BHSD]$")>;
21482148

21492149
// Bit manipulation
@@ -2154,7 +2154,7 @@ def : InstRW<[V2Write_2cyc_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ$")>;
21542154

21552155
// Count/reverse bits
21562156
def : InstRW<[V2Write_2cyc_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]$",
2157-
"^(CLS|CLZ|CNT)_ZPmZ_UNDEF_[BHSD]$")>;
2157+
"^(CLS|CLZ|CNT)_ZPmZ_[BHSD]_UNDEF$")>;
21582158

21592159
// Broadcast logical bitmask immediate to vector
21602160
def : InstRW<[V2Write_2cyc_1V], (instrs DUPM_ZI)>;
@@ -2207,11 +2207,11 @@ def : InstRW<[V2Write_2cyc_1V], (instregex "^CPY_ZPm[IV]_[BHSD]$",
22072207

22082208
// Divides, 32 bit
22092209
def : InstRW<[V2Write_12cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_S$",
2210-
"^[SU]DIV_ZPZZ_UNDEF_S$")>;
2210+
"^[SU]DIV_ZPZZ_S_UNDEF$")>;
22112211

22122212
// Divides, 64 bit
22132213
def : InstRW<[V2Write_20cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_D$",
2214-
"^[SU]DIV_ZPZZ_UNDEF_D$")>;
2214+
"^[SU]DIV_ZPZZ_D_UNDEF$")>;
22152215

22162216
// Dot product, 8 bit
22172217
def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_S$")>;
@@ -2273,12 +2273,12 @@ def : InstRW<[V2Write_2cyc_1V],
22732273
"^(AND|BIC|EOR|ORR)_ZZZ$",
22742274
"^EOR(BT|TB)_ZZZ_[BHSD]$",
22752275
"^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]$",
2276-
"^NOT_ZPmZ_UNDEF_[BHSD]$")>;
2276+
"^NOT_ZPmZ_[BHSD]_UNDEF$")>;
22772277

22782278
// Max/min, basic and pairwise
22792279
def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]$",
22802280
"^[SU](MAX|MIN)P?_ZPmZ_[BHSD]$",
2281-
"^[SU](MAX|MIN)_ZPZZ_UNDEF_[BHSD]$")>;
2281+
"^[SU](MAX|MIN)_ZPZZ_[BHSD]_UNDEF$")>;
22822282

22832283
// Matching operations
22842284
// FIXME: SOG p. 44, n. 5: If the consuming instruction has a flag source, the
@@ -2294,29 +2294,29 @@ def : InstRW<[V2Write_2cyc_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$",
22942294

22952295
// Multiply, B, H, S element size
22962296
def : InstRW<[V2Write_4cyc_1V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]$",
2297-
"^MUL_ZPZZ_UNDEF_[BHS]$",
2297+
"^MUL_ZPZZ_[BHS]_UNDEF$",
22982298
"^[SU]MULH_(ZPmZ|ZZZ)_[BHS]$",
2299-
"^[SU]MULH_ZPZZ_UNDEF_[BHS]$")>;
2299+
"^[SU]MULH_ZPZZ_[BHS]_UNDEF$")>;
23002300

23012301
// Multiply, D element size
23022302
def : InstRW<[V2Write_5cyc_2V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D$",
2303-
"^MUL_ZPZZ_UNDEF_D$",
2303+
"^MUL_ZPZZ_D_UNDEF$",
23042304
"^[SU]MULH_(ZPmZ|ZZZ)_D$",
2305-
"^[SU]MULH_ZPZZ_UNDEF_D$")>;
2305+
"^[SU]MULH_ZPZZ_D_UNDEF$")>;
23062306

23072307
// Multiply long
23082308
def : InstRW<[V2Write_4cyc_1V02], (instregex "^[SU]MULL[BT]_ZZZI_[SD]$",
23092309
"^[SU]MULL[BT]_ZZZ_[HSD]$")>;
23102310

23112311
// Multiply accumulate, B, H, S element size
23122312
def : InstRW<[V2Wr_ZMABHS, V2Rd_ZMABHS],
2313-
(instregex "^ML[AS]_ZZZI_[HS]$", "^ML[AS]_ZPZZZ_UNDEF_[BHS]$")>;
2313+
(instregex "^ML[AS]_ZZZI_[HS]$", "^ML[AS]_ZPZZZ_[BHS]_UNDEF$")>;
23142314
def : InstRW<[V2Wr_ZMABHS, ReadDefault, V2Rd_ZMABHS],
23152315
(instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]$")>;
23162316

23172317
// Multiply accumulate, D element size
23182318
def : InstRW<[V2Wr_ZMAD, V2Rd_ZMAD],
2319-
(instregex "^ML[AS]_ZZZI_D$", "^ML[AS]_ZPZZZ_UNDEF_D$")>;
2319+
(instregex "^ML[AS]_ZZZI_D$", "^ML[AS]_ZPZZZ_D_UNDEF$")>;
23202320
def : InstRW<[V2Wr_ZMAD, ReadDefault, V2Rd_ZMAD],
23212321
(instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D$")>;
23222322

@@ -2368,7 +2368,7 @@ def : InstRW<[V2Write_2cyc_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI$")>;
23682368

23692369
// Reciprocal estimate
23702370
def : InstRW<[V2Write_4cyc_2V02], (instrs URECPE_ZPmZ_S, URSQRTE_ZPmZ_S,
2371-
URECPE_ZPmZ_UNDEF_S, URSQRTE_ZPmZ_UNDEF_S)>;
2371+
URECPE_ZPmZ_S_UNDEF, URSQRTE_ZPmZ_S_UNDEF)>;
23722372

23732373
// Reduction, arithmetic, B form
23742374
def : InstRW<[V2Write_9cyc_2V_4V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;
@@ -2414,16 +2414,16 @@ def : InstRW<[V2Write_2cyc_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>;
24142414

24152415
// Floating point absolute value/difference
24162416
def : InstRW<[V2Write_2cyc_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]$",
2417-
"^FABD_ZPZZ_UNDEF_[HSD]$",
2418-
"^FABS_ZPmZ_UNDEF_[HSD]$")>;
2417+
"^FABD_ZPZZ_[HSD]_UNDEF$",
2418+
"^FABS_ZPmZ_[HSD]_UNDEF$")>;
24192419

24202420
// Floating point arithmetic
24212421
def : InstRW<[V2Write_2cyc_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]$",
2422-
"^F(ADD|SUB)_ZPZ[IZ]_UNDEF_[HSD]$",
2422+
"^F(ADD|SUB)_ZPZ[IZ]_[HSD]_UNDEF$",
24232423
"^FADDP_ZPmZZ_[HSD]$",
24242424
"^FNEG_ZPmZ(_UNDEF)?_[HSD]$",
24252425
"^FSUBR_ZPm[IZ]_[HSD]$",
2426-
"^FSUBR_ZPZI_UNDEF_[HSD]$")>;
2426+
"^FSUBR_ZPZI_[HSD]_UNDEF$")>;
24272427

24282428
// Floating point associative add, F16
24292429
def : InstRW<[V2Write_10cyc_1V1_9rc], (instrs FADDA_VPZ_H)>;
@@ -2486,51 +2486,51 @@ def : InstRW<[V2Write_2cyc_1V], (instregex "^FCPY_ZPmI_[HSD]$",
24862486

24872487
// Floating point divide, F16
24882488
def : InstRW<[V2Write_13cyc_1V02_12rc], (instregex "^FDIVR?_ZPmZ_H$",
2489-
"^FDIV_ZPZZ_UNDEF_H$")>;
2489+
"^FDIV_ZPZZ_H_UNDEF$")>;
24902490

24912491
// Floating point divide, F32
24922492
def : InstRW<[V2Write_10cyc_1V02_9rc], (instregex "^FDIVR?_ZPmZ_S$",
2493-
"^FDIV_ZPZZ_UNDEF_S$")>;
2493+
"^FDIV_ZPZZ_S_UNDEF$")>;
24942494

24952495
// Floating point divide, F64
24962496
def : InstRW<[V2Write_15cyc_1V02_14rc], (instregex "^FDIVR?_ZPmZ_D$",
2497-
"^FDIV_ZPZZ_UNDEF_D$")>;
2497+
"^FDIV_ZPZZ_D_UNDEF$")>;
24982498

24992499
// Floating point min/max pairwise
25002500
def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]$")>;
25012501

25022502
// Floating point min/max
25032503
def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]$",
2504-
"^F(MAX|MIN)(NM)?_ZPZ[IZ]_UNDEF_[HSD]$")>;
2504+
"^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]_UNDEF$")>;
25052505

25062506
// Floating point multiply
25072507
def : InstRW<[V2Write_3cyc_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]$",
2508-
"^FMULX_ZPZZ_UNDEF_[HSD]$",
2508+
"^FMULX_ZPZZ_[HSD]_UNDEF$",
25092509
"^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]$",
2510-
"^FMUL_ZPZ[IZ]_UNDEF_[HSD]$")>;
2510+
"^FMUL_ZPZ[IZ]_[HSD]_UNDEF$")>;
25112511

25122512
// Floating point multiply accumulate
25132513
def : InstRW<[V2Wr_ZFMA, ReadDefault, V2Rd_ZFMA],
25142514
(instregex "^FN?ML[AS]_ZPmZZ_[HSD]$",
25152515
"^FN?(MAD|MSB)_ZPmZZ_[HSD]$")>;
25162516
def : InstRW<[V2Wr_ZFMA, V2Rd_ZFMA],
25172517
(instregex "^FML[AS]_ZZZI_[HSD]$",
2518-
"^FN?ML[AS]_ZPZZZ_UNDEF_[HSD]$")>;
2518+
"^FN?ML[AS]_ZPZZZ_[HSD]_UNDEF$")>;
25192519

25202520
// Floating point multiply add/sub accumulate long
25212521
def : InstRW<[V2Wr_ZFMAL, V2Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>;
25222522

25232523
// Floating point reciprocal estimate, F16
25242524
def : InstRW<[V2Write_6cyc_4V02], (instrs FRECPE_ZZ_H, FRECPX_ZPmZ_H,
2525-
FRSQRTE_ZZ_H, FRECPX_ZPmZ_UNDEF_H)>;
2525+
FRSQRTE_ZZ_H, FRECPX_ZPmZ_H_UNDEF)>;
25262526

25272527
// Floating point reciprocal estimate, F32
25282528
def : InstRW<[V2Write_4cyc_2V02], (instrs FRECPE_ZZ_S, FRECPX_ZPmZ_S,
2529-
FRSQRTE_ZZ_S, FRECPX_ZPmZ_UNDEF_S)>;
2529+
FRSQRTE_ZZ_S, FRECPX_ZPmZ_S_UNDEF)>;
25302530

25312531
// Floating point reciprocal estimate, F64
25322532
def : InstRW<[V2Write_3cyc_1V02], (instrs FRECPE_ZZ_D, FRECPX_ZPmZ_D,
2533-
FRSQRTE_ZZ_D, FRECPX_ZPmZ_UNDEF_D)>;
2533+
FRSQRTE_ZZ_D, FRECPX_ZPmZ_D_UNDEF)>;
25342534

25352535
// Floating point reciprocal step
25362536
def : InstRW<[V2Write_4cyc_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>;
@@ -2557,13 +2557,13 @@ def : InstRW<[V2Write_4cyc_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_S$")
25572557
def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_D$")>;
25582558

25592559
// Floating point square root, F16
2560-
def : InstRW<[V2Write_13cyc_1V0_12rc], (instrs FSQRT_ZPmZ_H, FSQRT_ZPmZ_UNDEF_H)>;
2560+
def : InstRW<[V2Write_13cyc_1V0_12rc], (instrs FSQRT_ZPmZ_H, FSQRT_ZPmZ_H_UNDEF)>;
25612561

25622562
// Floating point square root, F32
2563-
def : InstRW<[V2Write_10cyc_1V0_9rc], (instrs FSQRT_ZPmZ_S, FSQRT_ZPmZ_UNDEF_S)>;
2563+
def : InstRW<[V2Write_10cyc_1V0_9rc], (instrs FSQRT_ZPmZ_S, FSQRT_ZPmZ_S_UNDEF)>;
25642564

25652565
// Floating point square root, F64
2566-
def : InstRW<[V2Write_16cyc_1V0_14rc], (instrs FSQRT_ZPmZ_D, FSQRT_ZPmZ_UNDEF_D)>;
2566+
def : InstRW<[V2Write_16cyc_1V0_14rc], (instrs FSQRT_ZPmZ_D, FSQRT_ZPmZ_D_UNDEF)>;
25672567

25682568
// Floating point trigonometric exponentiation
25692569
def : InstRW<[V2Write_3cyc_1V1], (instregex "^FEXPA_ZZ_[HSD]$")>;

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