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Merged main:c56bd7ab7934355ed19d4d3ec299b5784bf02379 into amd-gfx:02fd22716224
Local branch amd-gfx 02fd227 Merged main:4f873730d6ac1a8496cdef939cc451f178a864ee into amd-gfx:f078619cd03f Remote branch main c56bd7a [mlir][linalg] Enable masked vectorisation for depthwise convolutions (llvm#81625)
2 parents 02fd227 + c56bd7a commit de71bf8

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‎bolt/include/bolt/Core/MCPlusBuilder.h

Lines changed: 14 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -487,10 +487,9 @@ class MCPlusBuilder {
487487
llvm_unreachable("not implemented");
488488
}
489489

490-
virtual bool createDirectCall(MCInst &Inst, const MCSymbol *Target,
490+
virtual void createDirectCall(MCInst &Inst, const MCSymbol *Target,
491491
MCContext *Ctx, bool IsTailCall) {
492492
llvm_unreachable("not implemented");
493-
return false;
494493
}
495494

496495
virtual MCPhysReg getX86R11() const { llvm_unreachable("not implemented"); }
@@ -1534,15 +1533,13 @@ class MCPlusBuilder {
15341533
}
15351534

15361535
/// Create a no-op instruction.
1537-
virtual bool createNoop(MCInst &Inst) const {
1536+
virtual void createNoop(MCInst &Inst) const {
15381537
llvm_unreachable("not implemented");
1539-
return false;
15401538
}
15411539

15421540
/// Create a return instruction.
1543-
virtual bool createReturn(MCInst &Inst) const {
1541+
virtual void createReturn(MCInst &Inst) const {
15441542
llvm_unreachable("not implemented");
1545-
return false;
15461543
}
15471544

15481545
/// Store \p Target absolute address to \p RegName
@@ -1556,32 +1553,23 @@ class MCPlusBuilder {
15561553

15571554
/// Creates a new unconditional branch instruction in Inst and set its operand
15581555
/// to TBB.
1559-
///
1560-
/// Returns true on success.
1561-
virtual bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
1556+
virtual void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
15621557
MCContext *Ctx) const {
15631558
llvm_unreachable("not implemented");
1564-
return false;
15651559
}
15661560

15671561
/// Creates a new call instruction in Inst and sets its operand to
15681562
/// Target.
1569-
///
1570-
/// Returns true on success.
1571-
virtual bool createCall(MCInst &Inst, const MCSymbol *Target,
1563+
virtual void createCall(MCInst &Inst, const MCSymbol *Target,
15721564
MCContext *Ctx) {
15731565
llvm_unreachable("not implemented");
1574-
return false;
15751566
}
15761567

15771568
/// Creates a new tail call instruction in Inst and sets its operand to
15781569
/// Target.
1579-
///
1580-
/// Returns true on success.
1581-
virtual bool createTailCall(MCInst &Inst, const MCSymbol *Target,
1570+
virtual void createTailCall(MCInst &Inst, const MCSymbol *Target,
15821571
MCContext *Ctx) {
15831572
llvm_unreachable("not implemented");
1584-
return false;
15851573
}
15861574

15871575
virtual void createLongTailCall(InstructionListType &Seq,
@@ -1590,43 +1578,36 @@ class MCPlusBuilder {
15901578
}
15911579

15921580
/// Creates a trap instruction in Inst.
1593-
///
1594-
/// Returns true on success.
1595-
virtual bool createTrap(MCInst &Inst) const {
1581+
virtual void createTrap(MCInst &Inst) const {
15961582
llvm_unreachable("not implemented");
1597-
return false;
15981583
}
15991584

16001585
/// Creates an instruction to bump the stack pointer just like a call.
1601-
virtual bool createStackPointerIncrement(MCInst &Inst, int Size = 8,
1586+
virtual void createStackPointerIncrement(MCInst &Inst, int Size = 8,
16021587
bool NoFlagsClobber = false) const {
16031588
llvm_unreachable("not implemented");
1604-
return false;
16051589
}
16061590

16071591
/// Creates an instruction to move the stack pointer just like a ret.
1608-
virtual bool createStackPointerDecrement(MCInst &Inst, int Size = 8,
1592+
virtual void createStackPointerDecrement(MCInst &Inst, int Size = 8,
16091593
bool NoFlagsClobber = false) const {
16101594
llvm_unreachable("not implemented");
1611-
return false;
16121595
}
16131596

16141597
/// Create a store instruction using \p StackReg as the base register
16151598
/// and \p Offset as the displacement.
1616-
virtual bool createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg,
1599+
virtual void createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg,
16171600
int Offset, const MCPhysReg &SrcReg,
16181601
int Size) const {
16191602
llvm_unreachable("not implemented");
1620-
return false;
16211603
}
16221604

1623-
virtual bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
1605+
virtual void createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
16241606
const MCPhysReg &IndexReg, int64_t Offset,
16251607
const MCExpr *OffsetExpr,
16261608
const MCPhysReg &AddrSegmentReg,
16271609
const MCPhysReg &DstReg, int Size) const {
16281610
llvm_unreachable("not implemented");
1629-
return false;
16301611
}
16311612

16321613
virtual InstructionListType createLoadImmediate(const MCPhysReg Dest,
@@ -1636,32 +1617,27 @@ class MCPlusBuilder {
16361617

16371618
/// Create a fragment of code (sequence of instructions) that load a 32-bit
16381619
/// address from memory, zero-extends it to 64 and jump to it (indirect jump).
1639-
virtual bool
1620+
virtual void
16401621
createIJmp32Frag(SmallVectorImpl<MCInst> &Insts, const MCOperand &BaseReg,
16411622
const MCOperand &Scale, const MCOperand &IndexReg,
16421623
const MCOperand &Offset, const MCOperand &TmpReg) const {
16431624
llvm_unreachable("not implemented");
1644-
return false;
16451625
}
16461626

16471627
/// Create a load instruction using \p StackReg as the base register
16481628
/// and \p Offset as the displacement.
1649-
virtual bool createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
1629+
virtual void createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
16501630
int Offset, const MCPhysReg &DstReg,
16511631
int Size) const {
16521632
llvm_unreachable("not implemented");
1653-
return false;
16541633
}
16551634

16561635
/// Creates a call frame pseudo instruction. A single operand identifies which
16571636
/// MCCFIInstruction this MCInst is referring to.
1658-
///
1659-
/// Returns true on success.
1660-
virtual bool createCFI(MCInst &Inst, int64_t Offset) const {
1637+
virtual void createCFI(MCInst &Inst, int64_t Offset) const {
16611638
Inst.clear();
16621639
Inst.setOpcode(TargetOpcode::CFI_INSTRUCTION);
16631640
Inst.addOperand(MCOperand::createImm(Offset));
1664-
return true;
16651641
}
16661642

16671643
/// Create an inline version of memcpy(dest, src, 1).

‎bolt/lib/Passes/BinaryPasses.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1056,10 +1056,9 @@ void Peepholes::addTailcallTraps(BinaryFunction &Function) {
10561056
MCInst *Inst = BB.getLastNonPseudoInstr();
10571057
if (Inst && MIB->isTailCall(*Inst) && MIB->isIndirectBranch(*Inst)) {
10581058
MCInst Trap;
1059-
if (MIB->createTrap(Trap)) {
1060-
BB.addInstruction(Trap);
1061-
++TailCallTraps;
1062-
}
1059+
MIB->createTrap(Trap);
1060+
BB.addInstruction(Trap);
1061+
++TailCallTraps;
10631062
}
10641063
}
10651064
}

‎bolt/lib/Passes/ShrinkWrapping.cpp

Lines changed: 15 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -680,16 +680,15 @@ void StackLayoutModifier::performChanges() {
680680
if (StackPtrReg != BC.MIB->getFramePointer())
681681
Adjustment = -Adjustment;
682682
if (IsLoad)
683-
Success = BC.MIB->createRestoreFromStack(
684-
Inst, StackPtrReg, StackOffset + Adjustment, Reg, Size);
683+
BC.MIB->createRestoreFromStack(Inst, StackPtrReg,
684+
StackOffset + Adjustment, Reg, Size);
685685
else if (IsStore)
686-
Success = BC.MIB->createSaveToStack(
687-
Inst, StackPtrReg, StackOffset + Adjustment, Reg, Size);
686+
BC.MIB->createSaveToStack(Inst, StackPtrReg, StackOffset + Adjustment,
687+
Reg, Size);
688688
LLVM_DEBUG({
689689
dbgs() << "Adjusted instruction: ";
690690
Inst.dump();
691691
});
692-
assert(Success);
693692
}
694693
}
695694
}
@@ -1653,19 +1652,13 @@ Expected<MCInst> ShrinkWrapping::createStackAccess(int SPVal, int FPVal,
16531652
if (SPVal != StackPointerTracking::SUPERPOSITION &&
16541653
SPVal != StackPointerTracking::EMPTY) {
16551654
if (FIE.IsLoad) {
1656-
if (!BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getStackPointer(),
1657-
FIE.StackOffset - SPVal, FIE.RegOrImm,
1658-
FIE.Size)) {
1659-
return createFatalBOLTError(
1660-
"createRestoreFromStack: not supported on this platform\n");
1661-
}
1662-
} else {
1663-
if (!BC.MIB->createSaveToStack(NewInst, BC.MIB->getStackPointer(),
1655+
BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getStackPointer(),
16641656
FIE.StackOffset - SPVal, FIE.RegOrImm,
1665-
FIE.Size)) {
1666-
return createFatalBOLTError(
1667-
"createSaveToStack: not supported on this platform\n");
1668-
}
1657+
FIE.Size);
1658+
} else {
1659+
BC.MIB->createSaveToStack(NewInst, BC.MIB->getStackPointer(),
1660+
FIE.StackOffset - SPVal, FIE.RegOrImm,
1661+
FIE.Size);
16691662
}
16701663
if (CreatePushOrPop)
16711664
BC.MIB->changeToPushOrPop(NewInst);
@@ -1675,19 +1668,12 @@ Expected<MCInst> ShrinkWrapping::createStackAccess(int SPVal, int FPVal,
16751668
FPVal != StackPointerTracking::EMPTY);
16761669

16771670
if (FIE.IsLoad) {
1678-
if (!BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getFramePointer(),
1679-
FIE.StackOffset - FPVal, FIE.RegOrImm,
1680-
FIE.Size)) {
1681-
return createFatalBOLTError(
1682-
"createRestoreFromStack: not supported on this platform\n");
1683-
}
1684-
} else {
1685-
if (!BC.MIB->createSaveToStack(NewInst, BC.MIB->getFramePointer(),
1671+
BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getFramePointer(),
16861672
FIE.StackOffset - FPVal, FIE.RegOrImm,
1687-
FIE.Size)) {
1688-
return createFatalBOLTError(
1689-
"createSaveToStack: not supported on this platform\n");
1690-
}
1673+
FIE.Size);
1674+
} else {
1675+
BC.MIB->createSaveToStack(NewInst, BC.MIB->getFramePointer(),
1676+
FIE.StackOffset - FPVal, FIE.RegOrImm, FIE.Size);
16911677
}
16921678
return NewInst;
16931679
}

‎bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

Lines changed: 8 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1026,7 +1026,7 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
10261026
return Code;
10271027
}
10281028

1029-
bool createTailCall(MCInst &Inst, const MCSymbol *Target,
1029+
void createTailCall(MCInst &Inst, const MCSymbol *Target,
10301030
MCContext *Ctx) override {
10311031
return createDirectCall(Inst, Target, Ctx, /*IsTailCall*/ true);
10321032
}
@@ -1036,11 +1036,10 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
10361036
createShortJmp(Seq, Target, Ctx, /*IsTailCall*/ true);
10371037
}
10381038

1039-
bool createTrap(MCInst &Inst) const override {
1039+
void createTrap(MCInst &Inst) const override {
10401040
Inst.clear();
10411041
Inst.setOpcode(AArch64::BRK);
10421042
Inst.addOperand(MCOperand::createImm(1));
1043-
return true;
10441043
}
10451044

10461045
bool convertJmpToTailCall(MCInst &Inst) override {
@@ -1068,16 +1067,15 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
10681067
Inst.getOperand(0).getImm() == 0;
10691068
}
10701069

1071-
bool createNoop(MCInst &Inst) const override {
1070+
void createNoop(MCInst &Inst) const override {
10721071
Inst.setOpcode(AArch64::HINT);
10731072
Inst.clear();
10741073
Inst.addOperand(MCOperand::createImm(0));
1075-
return true;
10761074
}
10771075

10781076
bool mayStore(const MCInst &Inst) const override { return false; }
10791077

1080-
bool createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
1078+
void createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
10811079
bool IsTailCall) override {
10821080
Inst.setOpcode(IsTailCall ? AArch64::B : AArch64::BL);
10831081
Inst.clear();
@@ -1086,7 +1084,6 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
10861084
*Ctx, 0)));
10871085
if (IsTailCall)
10881086
convertJmpToTailCall(Inst);
1089-
return true;
10901087
}
10911088

10921089
bool analyzeBranch(InstructionIterator Begin, InstructionIterator End,
@@ -1293,14 +1290,13 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
12931290
return true;
12941291
}
12951292

1296-
bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
1293+
void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
12971294
MCContext *Ctx) const override {
12981295
Inst.setOpcode(AArch64::B);
12991296
Inst.clear();
13001297
Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
13011298
Inst, MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx),
13021299
*Ctx, 0)));
1303-
return true;
13041300
}
13051301

13061302
bool shouldRecordCodeRelocation(uint64_t RelType) const override {
@@ -1353,14 +1349,13 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
13531349
return StringRef("\0\0\0\0", 4);
13541350
}
13551351

1356-
bool createReturn(MCInst &Inst) const override {
1352+
void createReturn(MCInst &Inst) const override {
13571353
Inst.setOpcode(AArch64::RET);
13581354
Inst.clear();
13591355
Inst.addOperand(MCOperand::createReg(AArch64::LR));
1360-
return true;
13611356
}
13621357

1363-
bool createStackPointerIncrement(
1358+
void createStackPointerIncrement(
13641359
MCInst &Inst, int Size,
13651360
bool NoFlagsClobber = false /*unused for AArch64*/) const override {
13661361
Inst.setOpcode(AArch64::SUBXri);
@@ -1369,10 +1364,9 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
13691364
Inst.addOperand(MCOperand::createReg(AArch64::SP));
13701365
Inst.addOperand(MCOperand::createImm(Size));
13711366
Inst.addOperand(MCOperand::createImm(0));
1372-
return true;
13731367
}
13741368

1375-
bool createStackPointerDecrement(
1369+
void createStackPointerDecrement(
13761370
MCInst &Inst, int Size,
13771371
bool NoFlagsClobber = false /*unused for AArch64*/) const override {
13781372
Inst.setOpcode(AArch64::ADDXri);
@@ -1381,7 +1375,6 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
13811375
Inst.addOperand(MCOperand::createReg(AArch64::SP));
13821376
Inst.addOperand(MCOperand::createImm(Size));
13831377
Inst.addOperand(MCOperand::createImm(0));
1384-
return true;
13851378
}
13861379

13871380
void createIndirectBranch(MCInst &Inst, MCPhysReg MemBaseReg,

‎bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -219,46 +219,43 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
219219
return true;
220220
}
221221

222-
bool createReturn(MCInst &Inst) const override {
222+
void createReturn(MCInst &Inst) const override {
223223
// TODO "c.jr ra" when RVC is enabled
224224
Inst.setOpcode(RISCV::JALR);
225225
Inst.clear();
226226
Inst.addOperand(MCOperand::createReg(RISCV::X0));
227227
Inst.addOperand(MCOperand::createReg(RISCV::X1));
228228
Inst.addOperand(MCOperand::createImm(0));
229-
return true;
230229
}
231230

232-
bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
231+
void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
233232
MCContext *Ctx) const override {
234233
Inst.setOpcode(RISCV::JAL);
235234
Inst.clear();
236235
Inst.addOperand(MCOperand::createReg(RISCV::X0));
237236
Inst.addOperand(MCOperand::createExpr(
238237
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)));
239-
return true;
240238
}
241239

242240
StringRef getTrapFillValue() const override {
243241
return StringRef("\0\0\0\0", 4);
244242
}
245243

246-
bool createCall(unsigned Opcode, MCInst &Inst, const MCSymbol *Target,
244+
void createCall(unsigned Opcode, MCInst &Inst, const MCSymbol *Target,
247245
MCContext *Ctx) {
248246
Inst.setOpcode(Opcode);
249247
Inst.clear();
250248
Inst.addOperand(MCOperand::createExpr(RISCVMCExpr::create(
251249
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx),
252250
RISCVMCExpr::VK_RISCV_CALL, *Ctx)));
253-
return true;
254251
}
255252

256-
bool createCall(MCInst &Inst, const MCSymbol *Target,
253+
void createCall(MCInst &Inst, const MCSymbol *Target,
257254
MCContext *Ctx) override {
258255
return createCall(RISCV::PseudoCALL, Inst, Target, Ctx);
259256
}
260257

261-
bool createTailCall(MCInst &Inst, const MCSymbol *Target,
258+
void createTailCall(MCInst &Inst, const MCSymbol *Target,
262259
MCContext *Ctx) override {
263260
return createCall(RISCV::PseudoTAIL, Inst, Target, Ctx);
264261
}

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