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Centralise & tweak handling of SyncScope to SPIR-V translation (#2727)
This patch collects the mapping from LLVM SyncScope ID, which was spread out across multiple sites, into a single utility function. Furthermore, it realigns the mapping to match LLVM conventions, namely it defaults to System / CrossDevice (please see llvm/llvm-project#106429) for more context for the proposed changes.
1 parent b0690c1 commit 630a90a

17 files changed

+79
-105
lines changed

‎lib/SPIRV/OCLUtil.h

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -580,6 +580,30 @@ getOrCreateSwitchFunc(StringRef MapName, Value *V,
580580
return addCallInst(M, MapName, Ty, V, nullptr, InsertPoint);
581581
}
582582

583+
/// Maps LLVM SyncScope into SPIR-V Scope.
584+
///
585+
/// \param [in] Ctx Context for the LLVM SyncScope
586+
/// \param [in] Id SyncScope::ID value which needs to be mapped to SPIR-V Scope
587+
inline spv::Scope toSPIRVScope(const LLVMContext &Ctx, SyncScope::ID Id) {
588+
// We follow Clang/LLVM convention by which the default is System scope, which
589+
// in SPIR-V maps to CrossDevice scope. This is in order to ensure that the
590+
// resulting SPIR-V is conservatively correct (i.e. always works), under the
591+
// assumption that it is the responsibility of the higher level language to
592+
// choose a narrower scope, if desired.
593+
switch (Id) {
594+
case SyncScope::SingleThread:
595+
return spv::ScopeInvocation;
596+
case SyncScope::System:
597+
return spv::ScopeCrossDevice;
598+
default:
599+
SmallVector<StringRef> SSIDs;
600+
Ctx.getSyncScopeNames(SSIDs);
601+
spv::Scope S = ScopeCrossDevice; // Default to CrossDevice scope.
602+
OCLStrMemScopeMap::find(SSIDs[Id].str(), &S);
603+
return S;
604+
}
605+
}
606+
583607
/// Performs conversion from OpenCL memory_scope into SPIR-V Scope.
584608
///
585609
/// Supports both constant and non-constant values. To handle the latter case,

‎lib/SPIRV/SPIRVRegularizeLLVM.cpp

Lines changed: 3 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -715,14 +715,6 @@ bool SPIRVRegularizeLLVMBase::regularize() {
715715
// %1 = insertvalue { i32, i1 } undef, i32 %cmpxchg.res, 0
716716
// %2 = insertvalue { i32, i1 } %1, i1 %cmpxchg.success, 1
717717

718-
// To get memory scope argument we use Cmpxchg->getSyncScopeID()
719-
// but LLVM's cmpxchg instruction is not aware of OpenCL(or SPIR-V)
720-
// memory scope enumeration. If the scope is not set and assuming the
721-
// produced SPIR-V module will be consumed in an OpenCL environment,
722-
// we can use the same memory scope as OpenCL atomic functions that do
723-
// not have memory_scope argument, i.e. memory_scope_device. See the
724-
// OpenCL C specification p6.13.11. Atomic Functions
725-
726718
// cmpxchg LLVM instruction returns a pair {i32, i1}: the original
727719
// value and a flag indicating success (true) or failure (false).
728720
// OpAtomicCompareExchange SPIR-V instruction returns only the
@@ -733,15 +725,9 @@ bool SPIRVRegularizeLLVMBase::regularize() {
733725
// comparator, which matches with semantics of the flag returned by
734726
// cmpxchg.
735727
Value *Ptr = Cmpxchg->getPointerOperand();
736-
SmallVector<StringRef> SSIDs;
737-
Cmpxchg->getContext().getSyncScopeNames(SSIDs);
738-
739-
spv::Scope S;
740-
// Fill unknown syncscope value to default Device scope.
741-
if (!OCLStrMemScopeMap::find(SSIDs[Cmpxchg->getSyncScopeID()].str(),
742-
&S)) {
743-
S = ScopeDevice;
744-
}
728+
729+
spv::Scope S =
730+
toSPIRVScope(Cmpxchg->getContext(), Cmpxchg->getSyncScopeID());
745731
Value *MemoryScope = getInt32(M, S);
746732
auto SuccessOrder = static_cast<OCLMemOrderKind>(
747733
llvm::toCABI(Cmpxchg->getSuccessOrdering()));

‎lib/SPIRV/SPIRVWriter.cpp

Lines changed: 4 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1901,14 +1901,7 @@ static int transAtomicOrdering(llvm::AtomicOrdering Ordering) {
19011901

19021902
SPIRVValue *LLVMToSPIRVBase::transAtomicStore(StoreInst *ST,
19031903
SPIRVBasicBlock *BB) {
1904-
SmallVector<StringRef> SSIDs;
1905-
ST->getContext().getSyncScopeNames(SSIDs);
1906-
1907-
spv::Scope S;
1908-
// Fill unknown syncscope value to default Device scope.
1909-
if (!OCLStrMemScopeMap::find(SSIDs[ST->getSyncScopeID()].str(), &S)) {
1910-
S = ScopeDevice;
1911-
}
1904+
spv::Scope S = toSPIRVScope(ST->getContext(), ST->getSyncScopeID());
19121905

19131906
std::vector<Value *> Ops{ST->getPointerOperand(), getUInt32(M, S),
19141907
getUInt32(M, transAtomicOrdering(ST->getOrdering())),
@@ -1921,14 +1914,7 @@ SPIRVValue *LLVMToSPIRVBase::transAtomicStore(StoreInst *ST,
19211914

19221915
SPIRVValue *LLVMToSPIRVBase::transAtomicLoad(LoadInst *LD,
19231916
SPIRVBasicBlock *BB) {
1924-
SmallVector<StringRef> SSIDs;
1925-
LD->getContext().getSyncScopeNames(SSIDs);
1926-
1927-
spv::Scope S;
1928-
// Fill unknown syncscope value to default Device scope.
1929-
if (!OCLStrMemScopeMap::find(SSIDs[LD->getSyncScopeID()].str(), &S)) {
1930-
S = ScopeDevice;
1931-
}
1917+
spv::Scope S = toSPIRVScope(LD->getContext(), LD->getSyncScopeID());
19321918

19331919
std::vector<Value *> Ops{
19341920
LD->getPointerOperand(), getUInt32(M, S),
@@ -2587,21 +2573,7 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
25872573
auto MemSem = OCLMemOrderMap::map(static_cast<OCLMemOrderKind>(Ordering));
25882574
std::vector<Value *> Operands(4);
25892575
Operands[0] = ARMW->getPointerOperand();
2590-
// To get the memory scope argument we use ARMW->getSyncScopeID(), but
2591-
// atomicrmw LLVM instruction is not aware of OpenCL(or SPIR-V) memory scope
2592-
// enumeration. If the scope is not set and assuming the produced SPIR-V
2593-
// module will be consumed in an OpenCL environment, we can use the same
2594-
// memory scope as OpenCL atomic functions that don't have memory_scope
2595-
// argument i.e. memory_scope_device. See the OpenCL C specification
2596-
// p6.13.11. "Atomic Functions"
2597-
SmallVector<StringRef> SSIDs;
2598-
ARMW->getContext().getSyncScopeNames(SSIDs);
2599-
2600-
spv::Scope S;
2601-
// Fill unknown syncscope value to default Device scope.
2602-
if (!OCLStrMemScopeMap::find(SSIDs[ARMW->getSyncScopeID()].str(), &S)) {
2603-
S = ScopeDevice;
2604-
}
2576+
spv::Scope S = toSPIRVScope(ARMW->getContext(), ARMW->getSyncScopeID());
26052577
Operands[1] = getUInt32(M, S);
26062578
Operands[2] = getUInt32(M, MemSem);
26072579
Operands[3] = ARMW->getValOperand();
@@ -5212,13 +5184,7 @@ SPIRVValue *LLVMToSPIRVBase::transFenceInst(FenceInst *FI,
52125184
}
52135185

52145186
Module *M = FI->getParent()->getModule();
5215-
SmallVector<StringRef> SSIDs;
5216-
FI->getContext().getSyncScopeNames(SSIDs);
5217-
spv::Scope S;
5218-
// Treat all llvm.fence instructions as having CrossDevice scope by default
5219-
if (!OCLStrMemScopeMap::find(SSIDs[FI->getSyncScopeID()].str(), &S)) {
5220-
S = ScopeCrossDevice;
5221-
}
5187+
spv::Scope S = toSPIRVScope(FI->getContext(), FI->getSyncScopeID());
52225188

52235189
SPIRVValue *RetScope = transConstant(getUInt32(M, S));
52245190
SPIRVValue *Val = transConstant(getUInt32(M, MemorySemantics));

‎test/AtomicCompareExchange.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; RUN: spirv-val %t.spv
55

66
; CHECK-SPIRV: TypeInt [[Int:[0-9]+]] 32 0
7-
; CHECK-SPIRV: Constant [[Int]] [[MemScope_Device:[0-9]+]] 1
7+
; CHECK-SPIRV: Constant [[Int]] [[MemScope_CrossDevice:[0-9]+]] 0
88
; CHECK-SPIRV: Constant [[Int]] [[MemSemEqual_SeqCst:[0-9]+]] 16
99
; CHECK-SPIRV: Constant [[Int]] [[MemSemUnequal_Acquire:[0-9]+]] 2
1010
; CHECK-SPIRV: Constant [[Int]] [[Constant_456:[0-9]+]] 456
@@ -18,7 +18,7 @@
1818
; CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[Comparator:[0-9]+]]
1919

2020
; CHECK-SPIRV: Load [[Int]] [[Value:[0-9]+]] [[Value_ptr]]
21-
; CHECK-SPIRV: AtomicCompareExchange [[Int]] [[Res:[0-9]+]] [[Pointer]] [[MemScope_Device]]
21+
; CHECK-SPIRV: AtomicCompareExchange [[Int]] [[Res:[0-9]+]] [[Pointer]] [[MemScope_CrossDevice]]
2222
; CHECK-SPIRV-SAME: [[MemSemEqual_SeqCst]] [[MemSemUnequal_Acquire]] [[Value]] [[Comparator]]
2323
; CHECK-SPIRV: IEqual {{[0-9]+}} [[Success:[0-9]+]] [[Res]] [[Comparator]]
2424
; CHECK-SPIRV: CompositeInsert [[Struct]] [[Composite_0:[0-9]+]] [[Res]] [[UndefStruct]] 0
@@ -48,7 +48,7 @@ cmpxchg.continue: ; preds = %cmpxchg.store_expec
4848
; CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[Ptr:[0-9]+]]
4949
; CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[Store_ptr:[0-9]+]]
5050

51-
; CHECK-SPIRV: AtomicCompareExchange [[Int]] [[Res_1:[0-9]+]] [[Ptr]] [[MemScope_Device]]
51+
; CHECK-SPIRV: AtomicCompareExchange [[Int]] [[Res_1:[0-9]+]] [[Ptr]] [[MemScope_CrossDevice]]
5252
; CHECK-SPIRV-SAME: [[MemSemEqual_SeqCst]] [[MemSemUnequal_Acquire]] [[Constant_456]] [[Constant_128]]
5353
; CHECK-SPIRV: IEqual {{[0-9]+}} [[Success_1:[0-9]+]] [[Res_1]] [[Constant_128]]
5454
; CHECK-SPIRV: CompositeInsert [[Struct]] [[Composite:[0-9]+]] [[Res_1]] [[UndefStruct]] 0

‎test/atomic-load-store.ll

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,10 @@
33
; RUN: spirv-val %t.spv
44
; RUN: llvm-spirv -to-text %t.spv -o - | FileCheck %s
55

6-
; CHECK-DAG: Constant [[#]] [[#Relaxed:]] 0
7-
; CHECK-DAG: Constant [[#]] [[#DeviceScope:]] 1
8-
; CHECK-DAG: Constant [[#]] [[#Acquire:]] 2
6+
; CHECK-DAG: Constant [[#]] [[#CrossDeviceScope:]] 0
97
; CHECK-DAG: Constant [[#]] [[#Release:]] 4
108
; CHECK-DAG: Constant [[#]] [[#SequentiallyConsistent:]] 16
9+
; CHECK-DAG: Constant [[#]] [[#Acquire:]] 2
1110

1211
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
1312
target triple = "spir64"
@@ -18,18 +17,18 @@ entry:
1817
; CHECK: Variable [[#]] [[#PTR:]]
1918
%0 = alloca i32
2019

21-
; CHECK: AtomicStore [[#PTR]] [[#DeviceScope]] [[#Relaxed]] [[#]]
20+
; CHECK: AtomicStore [[#PTR]] [[#CrossDeviceScope]] {{.+}} [[#]]
2221
store atomic i32 0, ptr %0 monotonic, align 4
23-
; CHECK: AtomicStore [[#PTR]] [[#DeviceScope]] [[#Release]] [[#]]
22+
; CHECK: AtomicStore [[#PTR]] [[#CrossDeviceScope]] [[#Release]] [[#]]
2423
store atomic i32 0, ptr %0 release, align 4
25-
; CHECK: AtomicStore [[#PTR]] [[#DeviceScope]] [[#SequentiallyConsistent]] [[#]]
24+
; CHECK: AtomicStore [[#PTR]] [[#CrossDeviceScope]] [[#SequentiallyConsistent]] [[#]]
2625
store atomic i32 0, ptr %0 seq_cst, align 4
2726

28-
; CHECK: AtomicLoad [[#]] [[#]] [[#PTR]] [[#DeviceScope]] [[#Relaxed]]
27+
; CHECK: AtomicLoad [[#]] [[#]] [[#PTR]] [[#CrossDeviceScope]] {{.+}}
2928
%1 = load atomic i32, ptr %0 monotonic, align 4
30-
; CHECK: AtomicLoad [[#]] [[#]] [[#PTR]] [[#DeviceScope]] [[#Acquire]]
29+
; CHECK: AtomicLoad [[#]] [[#]] [[#PTR]] [[#CrossDeviceScope]] [[#Acquire]]
3130
%2 = load atomic i32, ptr %0 acquire, align 4
32-
; CHECK: AtomicLoad [[#]] [[#]] [[#PTR]] [[#DeviceScope]] [[#SequentiallyConsistent]]
31+
; CHECK: AtomicLoad [[#]] [[#]] [[#PTR]] [[#CrossDeviceScope]] [[#SequentiallyConsistent]]
3332
%3 = load atomic i32, ptr %0 seq_cst, align 4
3433
ret void
3534
}

‎test/atomicrmw.ll

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44
; RUN: llvm-spirv -to-text %t.spv -o - | FileCheck %s
55

66
; CHECK: TypeInt [[Int:[0-9]+]] 32 0
7-
; CHECK-DAG: Constant [[Int]] [[Scope_Device:[0-9]+]] 1 {{$}}
87
; CHECK-DAG: Constant [[Int]] [[MemSem_Relaxed:[0-9]+]] 0
98
; CHECK-DAG: Constant [[Int]] [[MemSem_Acquire:[0-9]+]] 2
109
; CHECK-DAG: Constant [[Int]] [[MemSem_Release:[0-9]+]] 4 {{$}}
@@ -26,37 +25,37 @@ target triple = "spir64"
2625
define dso_local spir_func void @test_atomicrmw() local_unnamed_addr #0 {
2726
entry:
2827
%0 = atomicrmw xchg ptr addrspace(1) @ui, i32 42 acq_rel
29-
; CHECK: AtomicExchange [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_AcquireRelease]] [[Value]]
28+
; CHECK: AtomicExchange [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_AcquireRelease]] [[Value]]
3029

3130
%1 = atomicrmw xchg ptr addrspace(1) @f, float 42.000000e+00 seq_cst
32-
; CHECK: AtomicExchange [[Float]] {{[0-9]+}} [[FPPointer]] [[Scope_Device]] [[MemSem_SequentiallyConsistent]] [[FPValue]]
31+
; CHECK: AtomicExchange [[Float]] {{[0-9]+}} [[FPPointer]] {{.+}} [[MemSem_SequentiallyConsistent]] [[FPValue]]
3332

3433
%2 = atomicrmw add ptr addrspace(1) @ui, i32 42 monotonic
35-
; CHECK: AtomicIAdd [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Relaxed]] [[Value]]
34+
; CHECK: AtomicIAdd [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_Relaxed]] [[Value]]
3635

3736
%3 = atomicrmw sub ptr addrspace(1) @ui, i32 42 acquire
38-
; CHECK: AtomicISub [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Acquire]] [[Value]]
37+
; CHECK: AtomicISub [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_Acquire]] [[Value]]
3938

4039
%4 = atomicrmw or ptr addrspace(1) @ui, i32 42 release
41-
; CHECK: AtomicOr [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Release]] [[Value]]
40+
; CHECK: AtomicOr [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_Release]] [[Value]]
4241

4342
%5 = atomicrmw xor ptr addrspace(1) @ui, i32 42 acq_rel
44-
; CHECK: AtomicXor [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_AcquireRelease]] [[Value]]
43+
; CHECK: AtomicXor [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_AcquireRelease]] [[Value]]
4544

4645
%6 = atomicrmw and ptr addrspace(1) @ui, i32 42 seq_cst
47-
; CHECK: AtomicAnd [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_SequentiallyConsistent]] [[Value]]
46+
; CHECK: AtomicAnd [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_SequentiallyConsistent]] [[Value]]
4847

4948
%7 = atomicrmw max ptr addrspace(1) @ui, i32 42 monotonic
50-
; CHECK: AtomicSMax [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Relaxed]] [[Value]]
49+
; CHECK: AtomicSMax [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_Relaxed]] [[Value]]
5150

5251
%8 = atomicrmw min ptr addrspace(1) @ui, i32 42 acquire
53-
; CHECK: AtomicSMin [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Acquire]] [[Value]]
52+
; CHECK: AtomicSMin [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_Acquire]] [[Value]]
5453

5554
%9 = atomicrmw umax ptr addrspace(1) @ui, i32 42 release
56-
; CHECK: AtomicUMax [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Release]] [[Value]]
55+
; CHECK: AtomicUMax [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_Release]] [[Value]]
5756

5857
%10 = atomicrmw umin ptr addrspace(1) @ui, i32 42 acq_rel
59-
; CHECK: AtomicUMin [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_AcquireRelease]] [[Value]]
58+
; CHECK: AtomicUMin [[Int]] {{[0-9]+}} [[Pointer]] {{.+}} [[MemSem_AcquireRelease]] [[Value]]
6059

6160
ret void
6261
}

‎test/extensions/EXT/SPV_EXT_shader_atomic_float_/atomicrmw_fadd_double.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
; CHECK-DAG: Extension "SPV_EXT_shader_atomic_float_add"
77
; CHECK-DAG: Capability AtomicFloat64AddEXT
88
; CHECK: TypeInt [[Int:[0-9]+]] 32 0
9-
; CHECK-DAG: Constant [[Int]] [[Scope_Device:[0-9]+]] 1 {{$}}
9+
; CHECK-DAG: Constant [[Int]] [[Scope_CrossDevice:[0-9]+]] 0 {{$}}
1010
; CHECK-DAG: Constant [[Int]] [[MemSem_SequentiallyConsistent:[0-9]+]] 16
1111
; CHECK: TypeFloat [[Double:[0-9]+]] 64
1212
; CHECK: Variable {{[0-9]+}} [[DoublePointer:[0-9]+]]
@@ -21,7 +21,7 @@ target triple = "spir64"
2121
define dso_local spir_func void @test_atomicrmw_fadd() local_unnamed_addr #0 {
2222
entry:
2323
%0 = atomicrmw fadd ptr addrspace(1) @f, double 42.000000e+00 seq_cst
24-
; CHECK: AtomicFAddEXT [[Double]] {{[0-9]+}} [[DoublePointer]] [[Scope_Device]] [[MemSem_SequentiallyConsistent]] [[DoubleValue]]
24+
; CHECK: AtomicFAddEXT [[Double]] {{[0-9]+}} [[DoublePointer]] [[Scope_CrossDevice]] [[MemSem_SequentiallyConsistent]] [[DoubleValue]]
2525

2626
ret void
2727
}

‎test/extensions/EXT/SPV_EXT_shader_atomic_float_/atomicrmw_fadd_float.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
; CHECK-DAG: Extension "SPV_EXT_shader_atomic_float_add"
77
; CHECK-DAG: Capability AtomicFloat32AddEXT
88
; CHECK: TypeInt [[Int:[0-9]+]] 32 0
9-
; CHECK-DAG: Constant [[Int]] [[Scope_Device:[0-9]+]] 1 {{$}}
9+
; CHECK-DAG: Constant [[Int]] [[Scope_CrossDevice:[0-9]+]] 0 {{$}}
1010
; CHECK-DAG: Constant [[Int]] [[MemSem_SequentiallyConsistent:[0-9]+]] 16
1111
; CHECK: TypeFloat [[Float:[0-9]+]] 32
1212
; CHECK: Variable {{[0-9]+}} [[FPPointer:[0-9]+]]
@@ -21,7 +21,7 @@ target triple = "spir64"
2121
define dso_local spir_func void @test_atomicrmw_fadd() local_unnamed_addr #0 {
2222
entry:
2323
%0 = atomicrmw fadd ptr addrspace(1) @f, float 42.000000e+00 seq_cst
24-
; CHECK: AtomicFAddEXT [[Float]] {{[0-9]+}} [[FPPointer]] [[Scope_Device]] [[MemSem_SequentiallyConsistent]] [[FPValue]]
24+
; CHECK: AtomicFAddEXT [[Float]] {{[0-9]+}} [[FPPointer]] [[Scope_CrossDevice]] [[MemSem_SequentiallyConsistent]] [[FPValue]]
2525

2626
ret void
2727
}

‎test/extensions/EXT/SPV_EXT_shader_atomic_float_/atomicrmw_fadd_half.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
; CHECK-DAG: Extension "SPV_EXT_shader_atomic_float_add"
88
; CHECK-DAG: Capability AtomicFloat16AddEXT
99
; CHECK: TypeInt [[TypeIntID:[0-9]+]] 32 0
10-
; CHECK-DAG: Constant [[TypeIntID]] [[ScopeDevice:[0-9]+]] 1 {{$}}
10+
; CHECK-DAG: Constant [[TypeIntID]] [[ScopeCrossDevice:[0-9]+]] 0 {{$}}
1111
; CHECK-DAG: Constant [[TypeIntID]] [[MemSem_SequentiallyConsistent:[0-9]+]] 16
1212
; CHECK: TypeFloat [[TypeFloatHalfID:[0-9]+]] 16
1313
; CHECK: Variable {{[0-9]+}} [[HalfPointer:[0-9]+]]
@@ -22,7 +22,7 @@ target triple = "spir64"
2222
define dso_local spir_func void @test_atomicrmw_fadd() local_unnamed_addr #0 {
2323
entry:
2424
%0 = atomicrmw fadd ptr addrspace(1) @f, half 42.000000e+00 seq_cst
25-
; CHECK: AtomicFAddEXT [[TypeFloatHalfID]] {{[0-9]+}} [[HalfPointer]] [[ScopeDevice]] [[MemSem_SequentiallyConsistent]] [[HalfValue]]
25+
; CHECK: AtomicFAddEXT [[TypeFloatHalfID]] {{[0-9]+}} [[HalfPointer]] [[ScopeCrossDevice]] [[MemSem_SequentiallyConsistent]] [[HalfValue]]
2626

2727
ret void
2828
}

‎test/extensions/EXT/SPV_EXT_shader_atomic_float_/atomicrmw_fsub_double.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
; CHECK-SPIRV-DAG: Extension "SPV_EXT_shader_atomic_float_add"
1010
; CHECK-SPIRV-DAG: Capability AtomicFloat64AddEXT
1111
; CHECK-SPIRV: TypeInt [[Int:[0-9]+]] 32 0
12-
; CHECK-SPIRV-DAG: Constant [[Int]] [[Scope_Device:[0-9]+]] 1 {{$}}
12+
; CHECK-SPIRV-DAG: Constant [[Int]] [[Scope_CrossDevice:[0-9]+]] 0 {{$}}
1313
; CHECK-SPIRV-DAG: Constant [[Int]] [[MemSem_SequentiallyConsistent:[0-9]+]] 16
1414
; CHECK-SPIRV: TypeFloat [[Double:[0-9]+]] 64
1515
; CHECK-SPIRV: Variable {{[0-9]+}} [[DoublePointer:[0-9]+]]
@@ -25,7 +25,7 @@ define dso_local spir_func void @test_atomicrmw_fadd() local_unnamed_addr #0 {
2525
entry:
2626
%0 = atomicrmw fsub ptr addrspace(1) @f, double 42.000000e+00 seq_cst
2727
; CHECK-SPIRV: FNegate [[Double]] [[NegateValue:[0-9]+]] [[DoubleValue]]
28-
; CHECK-SPIRV: AtomicFAddEXT [[Double]] {{[0-9]+}} [[DoublePointer]] [[Scope_Device]] [[MemSem_SequentiallyConsistent]] [[NegateValue]]
28+
; CHECK-SPIRV: AtomicFAddEXT [[Double]] {{[0-9]+}} [[DoublePointer]] [[Scope_CrossDevice]] [[MemSem_SequentiallyConsistent]] [[NegateValue]]
2929
; CHECK-LLVM: [[FNegateLLVM:%[0-9]+]] = fneg double 4.200000e+01
3030
; CHECK-LLVM: call spir_func double {{.*}}atomic_add{{.*}}(ptr addrspace(1) @f, double [[FNegateLLVM]])
3131
ret void

‎test/extensions/EXT/SPV_EXT_shader_atomic_float_/atomicrmw_fsub_float.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
; CHECK-SPIRV-DAG: Extension "SPV_EXT_shader_atomic_float_add"
1010
; CHECK-SPIRV-DAG: Capability AtomicFloat32AddEXT
1111
; CHECK-SPIRV: TypeInt [[Int:[0-9]+]] 32 0
12-
; CHECK-SPIRV-DAG: Constant [[Int]] [[Scope_Device:[0-9]+]] 1 {{$}}
12+
; CHECK-SPIRV-DAG: Constant [[Int]] [[Scope_CrossDevice:[0-9]+]] 0 {{$}}
1313
; CHECK-SPIRV-DAG: Constant [[Int]] [[MemSem_SequentiallyConsistent:[0-9]+]] 16
1414
; CHECK-SPIRV: TypeFloat [[Float:[0-9]+]] 32
1515
; CHECK-SPIRV: Variable {{[0-9]+}} [[FPPointer:[0-9]+]]
@@ -25,7 +25,7 @@ define dso_local spir_func void @test_atomicrmw_fadd() local_unnamed_addr #0 {
2525
entry:
2626
%0 = atomicrmw fsub ptr addrspace(1) @f, float 42.000000e+00 seq_cst
2727
; CHECK-SPIRV: FNegate [[Float]] [[NegateValue:[0-9]+]] [[FPValue]]
28-
; CHECK-SPIRV: AtomicFAddEXT [[Float]] {{[0-9]+}} [[FPPointer]] [[Scope_Device]] [[MemSem_SequentiallyConsistent]] [[NegateValue]]
28+
; CHECK-SPIRV: AtomicFAddEXT [[Float]] {{[0-9]+}} [[FPPointer]] [[Scope_CrossDevice]] [[MemSem_SequentiallyConsistent]] [[NegateValue]]
2929
; CHECK-LLVM: [[FNegateLLVM:%[0-9]+]] = fneg float 4.200000e+01
3030
; CHECK-LLVM: call spir_func float {{.*}}atomic_add{{.*}}(ptr addrspace(1) @f, float [[FNegateLLVM]])
3131
ret void

‎test/extensions/EXT/SPV_EXT_shader_atomic_float_/atomicrmw_fsub_half.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
; CHECK-SPIRV-DAG: Extension "SPV_EXT_shader_atomic_float_add"
1111
; CHECK-SPIRV-DAG: Capability AtomicFloat16AddEXT
1212
; CHECK-SPIRV: TypeInt [[Int:[0-9]+]] 32 0
13-
; CHECK-SPIRV-DAG: Constant [[Int]] [[ScopeDevice:[0-9]+]] 1 {{$}}
13+
; CHECK-SPIRV-DAG: Constant [[Int]] [[ScopeCrossDevice:[0-9]+]] 0 {{$}}
1414
; CHECK-SPIRV-DAG: Constant [[Int]] [[MemSem_SequentiallyConsistent:[0-9]+]] 16
1515
; CHECK-SPIRV: TypeFloat [[Half:[0-9]+]] 16
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; CHECK-SPIRV: Variable {{[0-9]+}} [[HalfPointer:[0-9]+]]
@@ -26,7 +26,7 @@ define dso_local spir_func void @test_atomicrmw_fadd() local_unnamed_addr #0 {
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entry:
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%0 = atomicrmw fsub ptr addrspace(1) @f, half 1.0e+00 seq_cst
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; CHECK-SPIRV: FNegate [[Half]] [[NegateValue:[0-9]+]] [[HalfValue]]
29-
; CHECK-SPIRV: AtomicFAddEXT [[Half]] {{[0-9]+}} [[HalfPointer]] [[ScopeDevice]] [[MemSem_SequentiallyConsistent]] [[NegateValue]]
29+
; CHECK-SPIRV: AtomicFAddEXT [[Half]] {{[0-9]+}} [[HalfPointer]] [[ScopeCrossDevice]] [[MemSem_SequentiallyConsistent]] [[NegateValue]]
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; CHECK-LLVM: [[FNegateLLVM:%[0-9]+]] = fneg half 0xH3C00
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; CHECK-LLVM: call spir_func half {{.*}}atomic_add{{.*}}(ptr addrspace(1) @f, half [[FNegateLLVM]])
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ret void

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