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[FMV][AArch64] Remove features which can be expressed as a combination of others. (llvm#113580)
Removes sve-bf16, sve-ebf16, and sve-i8mm since they are obsolete. One could write target_version("sve+bf16") instead of sve-bf16 for instance. Approved in ACLE as ARM-software/acle#353
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-44
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10 files changed

+22
-44
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‎clang/lib/Basic/Targets/AArch64.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -765,8 +765,6 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
765765
.Case("i8mm", HasMatMul)
766766
.Case("bf16", HasBFloat16)
767767
.Case("sve", FPU & SveMode)
768-
.Case("sve-bf16", FPU & SveMode && HasBFloat16)
769-
.Case("sve-i8mm", FPU & SveMode && HasMatMul)
770768
.Case("sve-b16b16", HasSVEB16B16)
771769
.Case("f32mm", FPU & SveMode && HasMatmulFP32)
772770
.Case("f64mm", FPU & SveMode && HasMatmulFP64)

‎clang/test/CodeGen/aarch64-cpu-supports-target.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,9 @@ int check_all_feature() {
99
return 3;
1010
else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts+dgh"))
1111
return 4;
12-
else if (__builtin_cpu_supports("i8mm+bf16+ebf16+rpres+sve+sve-bf16"))
12+
else if (__builtin_cpu_supports("i8mm+bf16+ebf16+rpres+sve"))
1313
return 5;
14-
else if (__builtin_cpu_supports("sve-ebf16+sve-i8mm+f32mm+f64mm"))
14+
else if (__builtin_cpu_supports("sve+ebf16+i8mm+f32mm+f64mm"))
1515
return 6;
1616
else if (__builtin_cpu_supports("sve2+sve2-aes+sve2-pmull128"))
1717
return 7;

‎clang/test/CodeGen/aarch64-fmv-dependencies.c

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -135,15 +135,6 @@ __attribute__((target_version("ssbs"))) int fmv(void) { return 0; }
135135
// CHECK: define dso_local i32 @fmv._Msve() #[[sve:[0-9]+]] {
136136
__attribute__((target_version("sve"))) int fmv(void) { return 0; }
137137

138-
// CHECK: define dso_local i32 @fmv._Msve-bf16() #[[sve_bf16_ebf16:[0-9]+]] {
139-
__attribute__((target_version("sve-bf16"))) int fmv(void) { return 0; }
140-
141-
// CHECK: define dso_local i32 @fmv._Msve-ebf16() #[[sve_bf16_ebf16:[0-9]+]] {
142-
__attribute__((target_version("sve-ebf16"))) int fmv(void) { return 0; }
143-
144-
// CHECK: define dso_local i32 @fmv._Msve-i8mm() #[[sve_i8mm:[0-9]+]] {
145-
__attribute__((target_version("sve-i8mm"))) int fmv(void) { return 0; }
146-
147138
// CHECK: define dso_local i32 @fmv._Msve2() #[[sve2:[0-9]+]] {
148139
__attribute__((target_version("sve2"))) int fmv(void) { return 0; }
149140

@@ -209,8 +200,6 @@ int caller() {
209200
// CHECK: attributes #[[sme2]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme2,+v8a"
210201
// CHECK: attributes #[[ssbs]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a"
211202
// CHECK: attributes #[[sve]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
212-
// CHECK: attributes #[[sve_bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
213-
// CHECK: attributes #[[sve_i8mm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a"
214203
// CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
215204
// CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a"
216205
// CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a"

‎clang/test/CodeGen/attr-target-version.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -27,11 +27,11 @@ int foo() {
2727
inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; }
2828
inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
2929
inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
30-
inline int __attribute__((target_version("dit+sve-ebf16"))) fmv_inline(void) { return 8; }
30+
inline int __attribute__((target_version("dit+ebf16"))) fmv_inline(void) { return 8; }
3131
inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; }
3232
inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; }
3333
inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; }
34-
inline int __attribute__((target_version("sve+sve-bf16"))) fmv_inline(void) { return 4; }
34+
inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; }
3535
inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; }
3636
inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; }
3737
inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; }
@@ -680,7 +680,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
680680
//
681681
//
682682
// CHECK: Function Attrs: noinline nounwind optnone
683-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMsve-ebf16
683+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMebf16
684684
// CHECK-SAME: () #[[ATTR28:[0-9]+]] {
685685
// CHECK-NEXT: entry:
686686
// CHECK-NEXT: ret i32 8
@@ -708,7 +708,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
708708
//
709709
//
710710
// CHECK: Function Attrs: noinline nounwind optnone
711-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsveMsve-bf16
711+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Msve
712712
// CHECK-SAME: () #[[ATTR32:[0-9]+]] {
713713
// CHECK-NEXT: entry:
714714
// CHECK-NEXT: ret i32 4
@@ -837,20 +837,20 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
837837
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
838838
// CHECK: resolver_else12:
839839
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
840-
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 4295098368
841-
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 4295098368
840+
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1207959552
841+
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1207959552
842842
// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]]
843843
// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
844844
// CHECK: resolver_return13:
845-
// CHECK-NEXT: ret ptr @fmv_inline._MditMsve-ebf16
845+
// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve
846846
// CHECK: resolver_else14:
847847
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
848-
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 3221225472
849-
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 3221225472
848+
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 268566528
849+
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 268566528
850850
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
851851
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
852852
// CHECK: resolver_return15:
853-
// CHECK-NEXT: ret ptr @fmv_inline._MsveMsve-bf16
853+
// CHECK-NEXT: ret ptr @fmv_inline._MditMebf16
854854
// CHECK: resolver_else16:
855855
// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
856856
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971520

‎clang/test/Sema/attr-target-clones-aarch64.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ void __attribute__((target_clones("default+sha3"))) warn1(void);
77

88
// expected-error@+2 {{'target_clones' and 'target_version' attributes are not compatible}}
99
// expected-note@+1 {{conflicting attribute is here}}
10-
void __attribute__((target_version("sve-bf16"), target_clones("sme+memtag"))) not_compat(void);
10+
void __attribute__((target_version("sve"), target_clones("sme+memtag"))) not_compat(void);
1111

1212
int redecl(void);
1313
int __attribute__((target_clones("frintts", "simd+fp", "default"))) redecl(void) { return 1; }
@@ -78,4 +78,4 @@ int useage(void) {
7878
// expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}}
7979
int __attribute__((target_clones("sve2-sha3+ssbs", "sm4"))) mv_after_use(void) { return 1; }
8080
// expected-error@+1 {{'main' cannot be a multiversioned function}}
81-
int __attribute__((target_clones("sve-i8mm"))) main() { return 1; }
81+
int __attribute__((target_clones("i8mm"))) main() { return 1; }

‎clang/test/SemaCXX/attr-target-version.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ double __attribute__((target_version("rcpc"))) diff_type1(void);
4949

5050
auto __attribute__((target_version("rcpc2"))) diff_type2(void) -> int { return 1; }
5151
//expected-error@+1 {{multiversioned function declaration has a different return type}}
52-
auto __attribute__((target_version("sve-bf16"))) diff_type2(void) -> long { return (long)1; }
52+
auto __attribute__((target_version("bf16"))) diff_type2(void) -> long { return (long)1; }
5353

5454
int __attribute__((target_version("fp16fml"))) diff_type3(void) noexcept(false) { return 1; }
5555
//expected-error@+2 {{exception specification in declaration does not match previous declaration}}
@@ -75,7 +75,7 @@ auto __attribute__((target_version("dpb2"))) ret3(void) -> int { return 1; }
7575
class Cls {
7676
__attribute__((target_version("rng"))) Cls();
7777
// expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support constructors}}
78-
__attribute__((target_version("sve-i8mm"))) ~Cls();
78+
__attribute__((target_version("i8mm"))) ~Cls();
7979
// expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support destructors}}
8080

8181
Cls &__attribute__((target_version("f32mm"))) operator=(const Cls &) = default;

‎compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53,9 +53,9 @@ enum CPUFeatures {
5353
FEAT_EBF16,
5454
FEAT_RPRES,
5555
FEAT_SVE,
56-
FEAT_SVE_BF16,
57-
FEAT_SVE_EBF16,
58-
FEAT_SVE_I8MM,
56+
RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy
57+
RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy
58+
RESERVED_FEAT_SVE_I8MM, // previously used and now ABI legacy
5959
FEAT_SVE_F32MM,
6060
FEAT_SVE_F64MM,
6161
FEAT_SVE2,

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -65,14 +65,10 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
6565
setCPUFeature(FEAT_I8MM);
6666
if (hwcap2 & HWCAP2_EBF16)
6767
setCPUFeature(FEAT_EBF16);
68-
if (hwcap2 & HWCAP2_SVE_EBF16)
69-
setCPUFeature(FEAT_SVE_EBF16);
7068
if (hwcap2 & HWCAP2_DGH)
7169
setCPUFeature(FEAT_DGH);
7270
if (hwcap2 & HWCAP2_FRINT)
7371
setCPUFeature(FEAT_FRINTTS);
74-
if (hwcap2 & HWCAP2_SVEI8MM)
75-
setCPUFeature(FEAT_SVE_I8MM);
7672
if (hwcap2 & HWCAP2_SVEF32MM)
7773
setCPUFeature(FEAT_SVE_F32MM);
7874
if (hwcap2 & HWCAP2_SVEF64MM)
@@ -119,8 +115,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
119115
setCPUFeature(FEAT_RCPC3);
120116
if (hwcap2 & HWCAP2_BF16)
121117
setCPUFeature(FEAT_BF16);
122-
if (hwcap2 & HWCAP2_SVEBF16)
123-
setCPUFeature(FEAT_SVE_BF16);
124118
if (hwcap & HWCAP_SVE)
125119
setCPUFeature(FEAT_SVE);
126120
if (hwcap2 & HWCAP2_SVE2)

‎llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53,9 +53,9 @@ enum CPUFeatures {
5353
FEAT_EBF16,
5454
FEAT_RPRES,
5555
FEAT_SVE,
56-
FEAT_SVE_BF16,
57-
FEAT_SVE_EBF16,
58-
FEAT_SVE_I8MM,
56+
RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy
57+
RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy
58+
RESERVED_FEAT_SVE_I8MM, // previously used and now ABI legacy
5959
FEAT_SVE_F32MM,
6060
FEAT_SVE_F64MM,
6161
FEAT_SVE2,

‎llvm/lib/Target/AArch64/AArch64FMV.td

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -81,9 +81,6 @@ def : FMVExtension<"sme-i16i64", "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
8181
def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
8282
def : FMVExtension<"ssbs", "FEAT_SSBS2", "+ssbs", 490>;
8383
def : FMVExtension<"sve", "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
84-
def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>;
85-
def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;
86-
def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>;
8784
def : FMVExtension<"sve2", "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
8885
def : FMVExtension<"sve2-aes", "FEAT_SVE_PMULL128", "+sve2,+sve,+aes,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
8986
def : FMVExtension<"sve2-bitperm", "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>;

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