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[TableGen] Use buildConstant to emit apply pattern immediates
Use ``MachineIRBuilder::buildConstant`` to emit typed immediates in 'apply' MIR patterns. This allows us to seamlessly handle vector cases, wherre a ``G_BUILD_VECTOR`` is needed to create a splat. Depends on llvm#65955
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-78
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10 files changed

+93
-78
lines changed

‎llvm/docs/GlobalISel/MIRPatterns.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -257,8 +257,8 @@ Common Pattern #3: Emitting a Constant Value
257257
When an immediate operand appears in an 'apply' pattern, the behavior
258258
depends on whether it's typed or not.
259259

260-
* If the immediate is typed, a ``G_CONSTANT`` is implicitly emitted
261-
(= a register operand is added to the instruction).
260+
* If the immediate is typed, ``MachineIRBuilder::buildConstant`` is used
261+
to create a ``G_CONSTANT``. A ``G_BUILD_VECTOR`` will be used for vectors.
262262
* If the immediate is untyped, a simple immediate is added
263263
(``MachineInstrBuilder::addImm``).
264264

‎llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -293,6 +293,11 @@ enum {
293293
/// - Opcode - The new opcode to use
294294
GIR_BuildMI,
295295

296+
/// Builds a constant and stores its result in a TempReg.
297+
/// - TempRegID - Temp Register to define.
298+
/// - Imm - The immediate to add
299+
GIR_BuildConstant,
300+
296301
/// Copy an operand to the specified instruction
297302
/// - NewInsnID - Instruction ID to modify
298303
/// - OldInsnID - Instruction ID to copy from

‎llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -941,6 +941,16 @@ bool GIMatchTableExecutor::executeMatchTable(
941941
break;
942942
}
943943

944+
case GIR_BuildConstant: {
945+
int64_t TempRegID = MatchTable[CurrentIdx++];
946+
int64_t Imm = MatchTable[CurrentIdx++];
947+
Builder.buildConstant(State.TempRegisters[TempRegID], Imm);
948+
DEBUG_WITH_TYPE(TgtExecutor::getName(),
949+
dbgs() << CurrentIdx << ": GIR_BuildConstant(TempReg["
950+
<< TempRegID << "], Imm=" << Imm << ")\n");
951+
break;
952+
}
953+
944954
case GIR_Copy: {
945955
int64_t NewInsnID = MatchTable[CurrentIdx++];
946956
int64_t OldInsnID = MatchTable[CurrentIdx++];

‎llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -48,25 +48,23 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
4848
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
4949
// CHECK-NEXT: GIR_Done,
5050
// CHECK-NEXT: // Label 0: @28
51-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ 67, // Rule ID 1 //
51+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ 59, // Rule ID 1 //
5252
// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled,
5353
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXT,
5454
// CHECK-NEXT: // MIs[0] a
5555
// CHECK-NEXT: // No operand predicates
5656
// CHECK-NEXT: // MIs[0] Operand 1
5757
// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
5858
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
59-
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_CONSTANT,
60-
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
61-
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/1, /*Type*/GILLT_s32, /*Imm*/0,
59+
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
6260
// CHECK-NEXT: // Combiner Rule #1: InstTest1
6361
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6462
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a
6563
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6664
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
6765
// CHECK-NEXT: GIR_Done,
68-
// CHECK-NEXT: // Label 1: @67
69-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ 96, // Rule ID 2 //
66+
// CHECK-NEXT: // Label 1: @59
67+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ 88, // Rule ID 2 //
7068
// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule2Enabled,
7169
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
7270
// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
@@ -79,7 +77,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
7977
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/GILLT_s32, /*Imm*/42,
8078
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
8179
// CHECK-NEXT: GIR_Done,
82-
// CHECK-NEXT: // Label 2: @96
80+
// CHECK-NEXT: // Label 2: @88
8381
// CHECK-NEXT: GIM_Reject,
8482
// CHECK-NEXT: };
8583
// CHECK-NEXT: return MatchTable0;

‎llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td

Lines changed: 9 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
2828

2929
// CHECK: const int64_t *GenMyCombiner::getMatchTable() const {
3030
// CHECK-NEXT: constexpr static int64_t MatchTable0[] = {
31-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 44, // Rule ID 0 //
31+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 36, // Rule ID 0 //
3232
// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
3333
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXT,
3434
// CHECK-NEXT: // MIs[0] root
@@ -40,52 +40,46 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
4040
// CHECK-NEXT: // No operand predicates
4141
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
4242
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43-
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_CONSTANT,
44-
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45-
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/1, /*Type*/GILLT_s32, /*Imm*/0,
43+
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
4644
// CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[0]]
4745
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4846
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root
4947
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5048
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
5149
// CHECK-NEXT: GIR_Done,
52-
// CHECK-NEXT: // Label 0: @44
53-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ 79, // Rule ID 1 //
50+
// CHECK-NEXT: // Label 0: @36
51+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ 63, // Rule ID 1 //
5452
// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
5553
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_TRUNC,
5654
// CHECK-NEXT: // MIs[0] root
5755
// CHECK-NEXT: // No operand predicates
5856
// CHECK-NEXT: // MIs[0] __Test0_match_0.z
5957
// CHECK-NEXT: // No operand predicates
6058
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
61-
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_CONSTANT,
62-
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
63-
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/1, /*Type*/GILLT_s32, /*Imm*/0,
59+
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
6460
// CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[1]]
6561
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6662
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root
6763
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6864
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
6965
// CHECK-NEXT: GIR_Done,
70-
// CHECK-NEXT: // Label 1: @79
71-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ 114, // Rule ID 2 //
66+
// CHECK-NEXT: // Label 1: @63
67+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ 90, // Rule ID 2 //
7268
// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
7369
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FPEXT,
7470
// CHECK-NEXT: // MIs[0] root
7571
// CHECK-NEXT: // No operand predicates
7672
// CHECK-NEXT: // MIs[0] __Test0_match_0.z
7773
// CHECK-NEXT: // No operand predicates
7874
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
79-
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_CONSTANT,
80-
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
81-
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/1, /*Type*/GILLT_s32, /*Imm*/0,
75+
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
8276
// CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[2]]
8377
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8478
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root
8579
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8680
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
8781
// CHECK-NEXT: GIR_Done,
88-
// CHECK-NEXT: // Label 2: @114
82+
// CHECK-NEXT: // Label 2: @90
8983
// CHECK-NEXT: GIM_Reject,
9084
// CHECK-NEXT: };
9185
// CHECK-NEXT: return MatchTable0;

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