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alex-tkzhuravl
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Revert "[AMDGPU] Precommit lit test for llvm#72140."
This reverts commit 8f7e9f3. Change-Id: Ibfb2589ae430d99ec16e482bad5f585f5af100b5
1 parent 675ba5e commit b633543

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-617
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4 files changed

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-617
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llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -8919,16 +8919,8 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg,
89198919
}
89208920

89218921
bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI) const {
8922-
// We need to handle instructions which may be inserted during register
8923-
// allocation to handle the prolog. The initial prolog instruction may have
8924-
// been separated from the start of the block by spills and copies inserted
8925-
// needed by the prolog.
8926-
uint16_t Opc = MI.getOpcode();
8927-
8928-
// FIXME: Copies inserted in the block prolog for live-range split should also
8929-
// be included.
8930-
return (isSpillOpcode(Opc) || (!MI.isTerminator() && Opc != AMDGPU::COPY &&
8931-
MI.modifiesRegister(AMDGPU::EXEC, &RI)));
8922+
return !MI.isTerminator() && MI.getOpcode() != AMDGPU::COPY &&
8923+
MI.modifiesRegister(AMDGPU::EXEC, &RI);
89328924
}
89338925

89348926
MachineInstrBuilder

llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,8 @@ define <4 x float> @waterfall_loop(<8 x i32> %vgpr_srd) {
144144
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
145145
; CHECK-NEXT: s_mov_b32 exec_lo, s21
146146
; CHECK-NEXT: ; %bb.2: ; in Loop: Header=BB0_1 Depth=1
147+
; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
148+
; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
147149
; CHECK-NEXT: s_or_saveexec_b32 s21, -1
148150
; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 ; 4-byte Folded Reload
149151
; CHECK-NEXT: s_mov_b32 exec_lo, s21
@@ -161,9 +163,6 @@ define <4 x float> @waterfall_loop(<8 x i32> %vgpr_srd) {
161163
; CHECK-NEXT: v_readlane_b32 s17, v2, 1
162164
; CHECK-NEXT: v_readlane_b32 s18, v2, 2
163165
; CHECK-NEXT: v_readlane_b32 s19, v2, 3
164-
; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
165-
; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
166-
; CHECK-NEXT: s_waitcnt vmcnt(0)
167166
; CHECK-NEXT: image_sample v0, v[0:1], s[8:15], s[16:19] dmask:0x1 dim:SQ_RSRC_IMG_2D
168167
; CHECK-NEXT: s_waitcnt vmcnt(0)
169168
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill

llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,8 +149,8 @@ define { i32, half } @call_split_type_used_outside_block_struct() #0 {
149149
; GCN-NEXT: s_addc_u32 s17, s17, func_struct@rel32@hi+12
150150
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
151151
; GCN-NEXT: v_readlane_b32 s30, v40, 0
152-
; GCN-NEXT: v_readlane_b32 s31, v40, 1
153152
; GCN-NEXT: v_mov_b32_e32 v1, v4
153+
; GCN-NEXT: v_readlane_b32 s31, v40, 1
154154
; GCN-NEXT: v_readlane_b32 s4, v40, 2
155155
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
156156
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload

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