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[RISCV] Add vector hasAndNot to enable optimizations (llvm#132438)
Enables transforms that emit the VANDN instruction. Co-authored-by: Craig Topper <[email protected]>
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+28
-20
lines changed

5 files changed

+28
-20
lines changed

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2052,14 +2052,22 @@ bool RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial(
20522052
bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
20532053
EVT VT = Y.getValueType();
20542054

2055-
// FIXME: Support vectors once we have tests.
20562055
if (VT.isVector())
20572056
return false;
20582057

20592058
return (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) &&
20602059
(!isa<ConstantSDNode>(Y) || cast<ConstantSDNode>(Y)->isOpaque());
20612060
}
20622061

2062+
bool RISCVTargetLowering::hasAndNot(SDValue Y) const {
2063+
EVT VT = Y.getValueType();
2064+
2065+
if (!VT.isVector())
2066+
return hasAndNotCompare(Y);
2067+
2068+
return Subtarget.hasStdExtZvkb();
2069+
}
2070+
20632071
bool RISCVTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
20642072
// Zbs provides BEXT[_I], which can be used with SEQZ/SNEZ as a bit test.
20652073
if (Subtarget.hasStdExtZbs())

llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -535,6 +535,7 @@ class RISCVTargetLowering : public TargetLowering {
535535
bool isCheapToSpeculateCtlz(Type *Ty) const override;
536536
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
537537
bool hasAndNotCompare(SDValue Y) const override;
538+
bool hasAndNot(SDValue Y) const override;
538539
bool hasBitTest(SDValue X, SDValue Y) const override;
539540
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
540541
SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -603,13 +603,16 @@ multiclass VPatUnarySDNode_V<SDPatternOperator op, string instruction_name,
603603
// This should match the logic in RISCVDAGToDAGISel::selectVSplat
604604
def riscv_splat_vector : PatFrag<(ops node:$rs1),
605605
(riscv_vmv_v_x_vl undef, node:$rs1, srcvalue)>;
606-
def riscv_vnot : PatFrag<(ops node:$rs1), (xor node:$rs1,
607-
(riscv_splat_vector -1))>;
606+
def allonessew8 : ImmLeaf<XLenVT, "return SignExtend64<8>(Imm) == -1LL;">;
607+
def allonessew16 : ImmLeaf<XLenVT, "return SignExtend64<16>(Imm) == -1LL;">;
608+
def allonessew32 : ImmLeaf<XLenVT, "return SignExtend64<32>(Imm) == -1LL;">;
609+
def allonessew64 : ImmLeaf<XLenVT, "return Imm == -1LL;">;
608610

609611
foreach vti = AllIntegerVectors in {
610612
let Predicates = !listconcat([HasStdExtZvkb],
611613
GetVTypePredicates<vti>.Predicates) in {
612-
def : Pat<(vti.Vector (and (riscv_vnot vti.RegClass:$rs1),
614+
def : Pat<(vti.Vector (and (xor vti.RegClass:$rs1,
615+
(riscv_splat_vector !cast<ImmLeaf>("allonessew"#vti.SEW))),
613616
vti.RegClass:$rs2)),
614617
(!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX)
615618
(vti.Vector (IMPLICIT_DEF)),
@@ -734,7 +737,7 @@ foreach vti = AllIntegerVectors in {
734737
GetVTypePredicates<vti>.Predicates) in {
735738
def : Pat<(vti.Vector (riscv_and_vl (riscv_xor_vl
736739
(vti.Vector vti.RegClass:$rs1),
737-
(riscv_splat_vector -1),
740+
(riscv_splat_vector !cast<ImmLeaf>("allonessew"#vti.SEW)),
738741
(vti.Vector vti.RegClass:$passthru),
739742
(vti.Mask VMV0:$vm),
740743
VLOpFrag),

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vandn.ll

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,8 @@ define <8 x i8> @not_signbit_mask_v8i8(<8 x i8> %a, <8 x i8> %b) {
1616
; CHECK-ZVKB-LABEL: not_signbit_mask_v8i8:
1717
; CHECK-ZVKB: # %bb.0:
1818
; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
19-
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
20-
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
21-
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
19+
; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 7
20+
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
2221
; CHECK-ZVKB-NEXT: ret
2322
%cond = icmp sgt <8 x i8> %a, splat (i8 -1)
2423
%r = select <8 x i1> %cond, <8 x i8> %b, <8 x i8> zeroinitializer
@@ -37,9 +36,8 @@ define <4 x i16> @not_signbit_mask_v4i16(<4 x i16> %a, <4 x i16> %b) {
3736
; CHECK-ZVKB-LABEL: not_signbit_mask_v4i16:
3837
; CHECK-ZVKB: # %bb.0:
3938
; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
40-
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
41-
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
42-
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
39+
; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 15
40+
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
4341
; CHECK-ZVKB-NEXT: ret
4442
%cond = icmp sgt <4 x i16> %a, splat (i16 -1)
4543
%r = select <4 x i1> %cond, <4 x i16> %b, <4 x i16> zeroinitializer
@@ -58,9 +56,8 @@ define <2 x i32> @not_signbit_mask_v2i32(<2 x i32> %a, <2 x i32> %b) {
5856
; CHECK-ZVKB-LABEL: not_signbit_mask_v2i32:
5957
; CHECK-ZVKB: # %bb.0:
6058
; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
61-
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
62-
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
63-
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
59+
; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 31
60+
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
6461
; CHECK-ZVKB-NEXT: ret
6562
%cond = icmp sgt <2 x i32> %a, splat (i32 -1)
6663
%r = select <2 x i1> %cond, <2 x i32> %b, <2 x i32> zeroinitializer
@@ -78,10 +75,10 @@ define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
7875
;
7976
; CHECK-ZVKB-LABEL: not_signbit_mask_v2i64:
8077
; CHECK-ZVKB: # %bb.0:
78+
; CHECK-ZVKB-NEXT: li a0, 63
8179
; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
82-
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
83-
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
84-
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
80+
; CHECK-ZVKB-NEXT: vsra.vx v8, v8, a0
81+
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
8582
; CHECK-ZVKB-NEXT: ret
8683
%cond = icmp sgt <2 x i64> %a, splat (i64 -1)
8784
%r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer

llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2580,9 +2580,8 @@ define <vscale x 1 x i8> @not_signbit_mask_nxv1i8(<vscale x 1 x i8> %a, <vscale
25802580
; CHECK-ZVKB-LABEL: not_signbit_mask_nxv1i8:
25812581
; CHECK-ZVKB: # %bb.0:
25822582
; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
2583-
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
2584-
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
2585-
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
2583+
; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 7
2584+
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
25862585
; CHECK-ZVKB-NEXT: ret
25872586
%cond = icmp sgt <vscale x 1 x i8> %a, splat (i8 -1)
25882587
%r = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> %b, <vscale x 1 x i8> zeroinitializer

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