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[NFC][InstCombine] Redundant-left-shift-input-masking: add some more undef tests
llvm-svn: 373248
1 parent 5c2c60d commit 0205be8

5 files changed

+115
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lines changed

‎llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,33 @@ define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
7171
ret <8 x i32> %t5
7272
}
7373

74+
define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) {
75+
; CHECK-LABEL: @t1_vec_splat_undef(
76+
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
77+
; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 undef, i32 1>, [[T0]]
78+
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
79+
; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]]
80+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
81+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
82+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
83+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
84+
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
85+
; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 0, i32 2147483647>
86+
; CHECK-NEXT: ret <8 x i32> [[T5]]
87+
;
88+
%t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
89+
%t1 = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 undef, i32 1>, %t0
90+
%t2 = add <8 x i32> %t1, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
91+
%t3 = and <8 x i32> %t2, %x
92+
%t4 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, %nbits
93+
call void @use8xi32(<8 x i32> %t0)
94+
call void @use8xi32(<8 x i32> %t1)
95+
call void @use8xi32(<8 x i32> %t2)
96+
call void @use8xi32(<8 x i32> %t4)
97+
%t5 = shl <8 x i32> %t3, %t4
98+
ret <8 x i32> %t5
99+
}
100+
74101
define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) {
75102
; CHECK-LABEL: @t2_vec_nonsplat(
76103
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -33, i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32>

‎llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,33 @@ define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
7171
ret <8 x i32> %t5
7272
}
7373

74+
define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) {
75+
; CHECK-LABEL: @t1_vec_splat_undef(
76+
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
77+
; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>, [[T0]]
78+
; CHECK-NEXT: [[T2:%.*]] = xor <8 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
79+
; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]]
80+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
81+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
82+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
83+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
84+
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
85+
; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 0, i32 2147483647>
86+
; CHECK-NEXT: ret <8 x i32> [[T5]]
87+
;
88+
%t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
89+
%t1 = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>, %t0
90+
%t2 = xor <8 x i32> %t1, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
91+
%t3 = and <8 x i32> %t2, %x
92+
%t4 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, %nbits
93+
call void @use8xi32(<8 x i32> %t0)
94+
call void @use8xi32(<8 x i32> %t1)
95+
call void @use8xi32(<8 x i32> %t2)
96+
call void @use8xi32(<8 x i32> %t4)
97+
%t5 = shl <8 x i32> %t3, %t4
98+
ret <8 x i32> %t5
99+
}
100+
74101
define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) {
75102
; CHECK-LABEL: @t2_vec_nonsplat(
76103
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -33, i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32>

‎llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-c.ll

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,25 @@ define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
5555
ret <8 x i32> %t3
5656
}
5757

58+
define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) {
59+
; CHECK-LABEL: @t1_vec_splat_undef(
60+
; CHECK-NEXT: [[T0:%.*]] = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>, [[NBITS:%.*]]
61+
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
62+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
63+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
64+
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T2]]
65+
; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 -1, i32 2147483647>
66+
; CHECK-NEXT: ret <8 x i32> [[T3]]
67+
;
68+
%t0 = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>, %nbits
69+
%t1 = and <8 x i32> %t0, %x
70+
%t2 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
71+
call void @use8xi32(<8 x i32> %t0)
72+
call void @use8xi32(<8 x i32> %t2)
73+
%t3 = shl <8 x i32> %t1, %t2 ; shift is smaller than mask
74+
ret <8 x i32> %t3
75+
}
76+
5877
define <8 x i32> @t1_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) {
5978
; CHECK-LABEL: @t1_vec_nonsplat(
6079
; CHECK-NEXT: [[T0:%.*]] = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]

‎llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,29 @@ define <8 x i32> @t2_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
6363
ret <8 x i32> %t4
6464
}
6565

66+
define <8 x i32> @t2_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) {
67+
; CHECK-LABEL: @t2_vec_splat_undef(
68+
; CHECK-NEXT: [[T0:%.*]] = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>, [[NBITS:%.*]]
69+
; CHECK-NEXT: [[T1:%.*]] = lshr <8 x i32> [[T0]], [[NBITS]]
70+
; CHECK-NEXT: [[T3:%.*]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
71+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
72+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
73+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]])
74+
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T3]]
75+
; CHECK-NEXT: [[T4:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 -1, i32 2147483647>
76+
; CHECK-NEXT: ret <8 x i32> [[T4]]
77+
;
78+
%t0 = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>, %nbits
79+
%t1 = lshr <8 x i32> %t0, %nbits
80+
%t2 = and <8 x i32> %t1, %x
81+
%t3 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
82+
call void @use8xi32(<8 x i32> %t0)
83+
call void @use8xi32(<8 x i32> %t1)
84+
call void @use8xi32(<8 x i32> %t3)
85+
%t4 = shl <8 x i32> %t2, %t3 ; shift is smaller than mask
86+
ret <8 x i32> %t4
87+
}
88+
6689
define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) {
6790
; CHECK-LABEL: @t2_vec_nonsplat(
6891
; CHECK-NEXT: [[T0:%.*]] = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]

‎llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-e.ll

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,25 @@ define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
5555
ret <8 x i32> %t3
5656
}
5757

58+
define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) {
59+
; CHECK-LABEL: @t1_vec_splat_undef(
60+
; CHECK-NEXT: [[T0:%.*]] = shl <8 x i32> [[X:%.*]], [[NBITS:%.*]]
61+
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
62+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
63+
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
64+
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X]], [[T2]]
65+
; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 -1, i32 2147483647>
66+
; CHECK-NEXT: ret <8 x i32> [[T3]]
67+
;
68+
%t0 = shl <8 x i32> %x, %nbits
69+
%t1 = lshr <8 x i32> %t0, %nbits
70+
%t2 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
71+
call void @use8xi32(<8 x i32> %t0)
72+
call void @use8xi32(<8 x i32> %t2)
73+
%t3 = shl <8 x i32> %t1, %t2 ; shift is smaller than mask
74+
ret <8 x i32> %t3
75+
}
76+
5877
define <8 x i32> @t1_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) {
5978
; CHECK-LABEL: @t1_vec_nonsplat(
6079
; CHECK-NEXT: [[T0:%.*]] = shl <8 x i32> [[X:%.*]], [[NBITS:%.*]]

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