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Update STM32L4xx HAL Drivers to v1.9.0
Included in STM32CubeL4 FW V1.13.0 Signed-off-by: Frederic.Pillon <[email protected]>
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‎system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 66 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
******************************************************************************
88
* @attention
99
*
10-
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10+
* <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
1111
*
1212
* Redistribution and use in source and binary forms, with or without modification,
1313
* are permitted provided that the following conditions are met:
@@ -444,12 +444,16 @@
444444
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
445445
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
446446
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
447-
#if defined(STM32G0)
448-
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
449-
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
450-
#else
451447
#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
452448
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
449+
450+
#if defined(STM32H7)
451+
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
452+
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
453+
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
454+
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
455+
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
456+
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
453457
#endif
454458

455459
/**
@@ -494,12 +498,12 @@
494498
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
495499
* @{
496500
*/
497-
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
501+
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
498502
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
499503
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
500504
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
501505
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
502-
#else
506+
#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
503507
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
504508
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
505509
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
@@ -540,16 +544,25 @@
540544
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
541545
#endif
542546

547+
#if defined(STM32H7)
548+
#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
549+
#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
550+
#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
551+
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
552+
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
553+
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
554+
#endif
555+
543556
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
544557
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
545558
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
546559

547-
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
560+
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
548561
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
549562
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
550563
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
551564
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
552-
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
565+
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
553566

554567
#if defined(STM32L1)
555568
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -605,7 +618,7 @@
605618
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
606619
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
607620
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
608-
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
621+
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
609622
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
610623
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
611624
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@@ -737,6 +750,16 @@
737750
* @{
738751
*/
739752
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
753+
754+
#if defined(STM32H7)
755+
#define I2S_IT_TXE I2S_IT_TXP
756+
#define I2S_IT_RXNE I2S_IT_RXP
757+
758+
#define I2S_FLAG_TXE I2S_FLAG_TXP
759+
#define I2S_FLAG_RXNE I2S_FLAG_RXP
760+
#define I2S_FLAG_FRE I2S_FLAG_TIFRE
761+
#endif
762+
740763
#if defined(STM32F7)
741764
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
742765
#endif
@@ -861,6 +884,21 @@
861884
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
862885
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
863886

887+
#if defined(STM32H7)
888+
889+
#define SPI_FLAG_TXE SPI_FLAG_TXP
890+
#define SPI_FLAG_RXNE SPI_FLAG_RXP
891+
892+
#define SPI_IT_TXE SPI_IT_TXP
893+
#define SPI_IT_RXNE SPI_IT_RXP
894+
895+
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
896+
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
897+
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
898+
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
899+
900+
#endif /* STM32H7 */
901+
864902
/**
865903
* @}
866904
*/
@@ -932,6 +970,10 @@
932970
#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
933971
#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
934972
#endif
973+
974+
#if defined(STM32F3)
975+
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
976+
#endif
935977
/**
936978
* @}
937979
*/
@@ -1288,6 +1330,14 @@
12881330
#define HAL_TIM_DMAError TIM_DMAError
12891331
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
12901332
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
1333+
#if defined(STM32H7)
1334+
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
1335+
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
1336+
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
1337+
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
1338+
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
1339+
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
1340+
#endif /* STM32H7 */
12911341
/**
12921342
* @}
12931343
*/
@@ -1770,6 +1820,10 @@
17701820
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
17711821
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
17721822

1823+
#if defined(STM32H7)
1824+
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
1825+
#endif
1826+
17731827
/**
17741828
* @}
17751829
*/
@@ -2165,19 +2219,6 @@
21652219
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
21662220
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
21672221

2168-
#if defined(STM32WB)
2169-
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
2170-
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
2171-
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
2172-
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
2173-
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
2174-
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
2175-
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
2176-
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
2177-
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
2178-
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
2179-
#define QSPI_IRQHandler QUADSPI_IRQHandler
2180-
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
21812222

21822223
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
21832224
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
@@ -2849,7 +2890,6 @@
28492890

28502891
#if defined(STM32L4)
28512892
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
2852-
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
28532893
#else
28542894
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
28552895
#endif
@@ -2977,7 +3017,7 @@
29773017
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
29783018
* @{
29793019
*/
2980-
#if defined (STM32G0)
3020+
#if defined (STM32L412xx) || defined (STM32L422xx)
29813021
#else
29823022
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
29833023
#endif
@@ -3109,6 +3149,7 @@
31093149
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
31103150
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
31113151
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
3152+
#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
31123153
#endif
31133154
/**
31143155
* @}
@@ -3298,10 +3339,7 @@
32983339
* @{
32993340
*/
33003341
#define __HAL_LTDC_LAYER LTDC_LAYER
3301-
#if defined(STM32F7)
3302-
#else
33033342
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
3304-
#endif
33053343
/**
33063344
* @}
33073345
*/

‎system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,8 @@
3636
*/
3737

3838
/* Define to prevent recursive inclusion -------------------------------------*/
39-
#ifndef __STM32_ASSERT_H
40-
#define __STM32_ASSERT_H
39+
#ifndef STM32_ASSERT_H
40+
#define STM32_ASSERT_H
4141

4242
#ifdef __cplusplus
4343
extern "C" {
@@ -67,7 +67,7 @@
6767
}
6868
#endif
6969

70-
#endif /* __STM32_ASSERT_H */
70+
#endif /* STM32_ASSERT_H */
7171

7272

7373
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h

Lines changed: 25 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,8 @@
3535
*/
3636

3737
/* Define to prevent recursive inclusion -------------------------------------*/
38-
#ifndef __STM32L4xx_HAL_H
39-
#define __STM32L4xx_HAL_H
38+
#ifndef STM32L4xx_HAL_H
39+
#define STM32L4xx_HAL_H
4040

4141
#ifdef __cplusplus
4242
extern "C" {
@@ -62,7 +62,7 @@
6262
/** @defgroup SYSCFG_BootMode Boot Mode
6363
* @{
6464
*/
65-
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
65+
#define SYSCFG_BOOT_MAINFLASH 0U
6666
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
6767

6868
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
@@ -72,7 +72,7 @@
7272
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
7373
/* STM32L496xx || STM32L4A6xx || */
7474
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
75-
75+
7676
#define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
7777

7878
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
@@ -188,8 +188,8 @@
188188
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
189189
* @{
190190
*/
191-
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
192-
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
191+
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */
192+
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
193193

194194
/**
195195
* @}
@@ -198,8 +198,8 @@
198198
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
199199
* @{
200200
*/
201-
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
202-
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
201+
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
202+
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
203203

204204
/**
205205
* @}
@@ -222,7 +222,7 @@
222222
*/
223223

224224
/** @brief Fast-mode Plus driving capability on a specific GPIO
225-
*/
225+
*/
226226
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
227227
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
228228
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
@@ -491,16 +491,16 @@
491491
* @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
492492
* @retval The new state of __FLAG__ (TRUE or FALSE).
493493
*/
494-
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
494+
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
495495

496496
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
497497
*/
498498
#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
499499

500500
/** @brief Fast-mode Plus driving capability enable/disable macros
501-
* @param __FASTMODEPLUS__ This parameter can be a value of :
501+
* @param __FASTMODEPLUS__ This parameter can be a value of :
502502
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
503-
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
503+
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
504504
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
505505
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
506506
*/
@@ -533,7 +533,7 @@
533533
((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
534534
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
535535

536-
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
536+
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))
537537

538538
#if defined(VREFBUF)
539539
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
@@ -542,7 +542,7 @@
542542
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
543543
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
544544

545-
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
545+
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
546546
#endif /* VREFBUF */
547547

548548
#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
@@ -566,6 +566,16 @@
566566
* @}
567567
*/
568568

569+
/* Exported variables --------------------------------------------------------*/
570+
571+
/** @addtogroup HAL_Exported_Variables
572+
* @{
573+
*/
574+
extern __IO uint32_t uwTick;
575+
/**
576+
* @}
577+
*/
578+
569579
/* Exported functions --------------------------------------------------------*/
570580

571581
/** @addtogroup HAL_Exported_Functions
@@ -664,6 +674,6 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
664674
}
665675
#endif
666676

667-
#endif /* __STM32L4xx_HAL_H */
677+
#endif /* STM32L4xx_HAL_H */
668678

669679
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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