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[ARM] MVE Vector Shifts
This adds basic lowering for MVE shifts. There are many shifts in MVE, but the instructions handled here are: VSHL (imm) VSHRu (imm) VSHRs (imm) VSHL (vector) VSHL (register) MVE, like NEON before it, doesn't have shift right by a vector (or register). We instead have to negate the amount and shift in the opposite direction. This means we have to convert any SHR's into a form of SHL (that is still signed or unsigned) with a negated condition and selecting from there. MVE still does have shifting by an immediate for SHL, ASR and LSR. This adds lowering for these and for register forms, which work well for shift lefts but may require an extra fold of neg(vdup(x)) -> vdup(neg(x)) to potentially work optimally for right shifts. Differential Revision: https://reviews.llvm.org/D64212 llvm-svn: 366056
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5 files changed

+508
-60
lines changed

5 files changed

+508
-60
lines changed

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

+8-5
Original file line numberDiff line numberDiff line change
@@ -250,6 +250,9 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
250250
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
251251
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
252252
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
253+
setOperationAction(ISD::SHL, VT, Custom);
254+
setOperationAction(ISD::SRA, VT, Custom);
255+
setOperationAction(ISD::SRL, VT, Custom);
253256
setOperationAction(ISD::SMIN, VT, Legal);
254257
setOperationAction(ISD::SMAX, VT, Legal);
255258
setOperationAction(ISD::UMIN, VT, Legal);
@@ -5718,10 +5721,11 @@ static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
57185721
return SDValue();
57195722

57205723
// We essentially have two forms here. Shift by an immediate and shift by a
5721-
// vector register. We cannot easily match shift by an immediate in tablegen
5722-
// so we do that here and generate a VSHLIMM/VSHRsIMM/VSHRuIMM. For shifting
5723-
// by a vector, we don't have VSHR, only VSHL (which can be signed or
5724-
// unsigned, and a negative shift indicates a shift right).
5724+
// vector register (there are also shift by a gpr, but that is just handled
5725+
// with a tablegen pattern). We cannot easily match shift by an immediate in
5726+
// tablegen so we do that here and generate a VSHLIMM/VSHRsIMM/VSHRuIMM.
5727+
// For shifting by a vector, we don't have VSHR, only VSHL (which can be
5728+
// signed or unsigned, and a negative shift indicates a shift right).
57255729
if (N->getOpcode() == ISD::SHL) {
57265730
if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
57275731
return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0),
@@ -12852,7 +12856,6 @@ static SDValue PerformShiftCombine(SDNode *N,
1285212856
if (!VT.isVector() || !TLI.isTypeLegal(VT))
1285312857
return SDValue();
1285412858

12855-
assert(ST->hasNEON() && "unexpected vector shift");
1285612859
int64_t Cnt;
1285712860

1285812861
switch (N->getOpcode()) {

‎llvm/lib/Target/ARM/ARMInstrInfo.td

+11
Original file line numberDiff line numberDiff line change
@@ -254,6 +254,17 @@ def ARMvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
254254
def ARMvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
255255
def ARMvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
256256

257+
258+
def SDTARMVSHIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
259+
SDTCisVT<2, i32>]>;
260+
def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
261+
SDTCisSameAs<0, 2>,]>;
262+
def ARMvshlImm : SDNode<"ARMISD::VSHLIMM", SDTARMVSHIMM>;
263+
def ARMvshrsImm : SDNode<"ARMISD::VSHRsIMM", SDTARMVSHIMM>;
264+
def ARMvshruImm : SDNode<"ARMISD::VSHRuIMM", SDTARMVSHIMM>;
265+
def ARMvshls : SDNode<"ARMISD::VSHLs", SDTARMVSH>;
266+
def ARMvshlu : SDNode<"ARMISD::VSHLu", SDTARMVSH>;
267+
257268
def ARMWLS : SDNode<"ARMISD::WLS", SDT_ARMWhileLoop,
258269
[SDNPHasChain]>;
259270

‎llvm/lib/Target/ARM/ARMInstrMVE.td

+55
Original file line numberDiff line numberDiff line change
@@ -2119,6 +2119,22 @@ defm MVE_VQSHL_by_vec : mve_shift_by_vec_multi<"vqshl", 0b1, 0b0>;
21192119
defm MVE_VQRSHL_by_vec : mve_shift_by_vec_multi<"vqrshl", 0b1, 0b1>;
21202120
defm MVE_VRSHL_by_vec : mve_shift_by_vec_multi<"vrshl", 0b0, 0b1>;
21212121

2122+
let Predicates = [HasMVEInt] in {
2123+
def : Pat<(v4i32 (ARMvshlu (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn))),
2124+
(v4i32 (MVE_VSHL_by_vecu32 (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)))>;
2125+
def : Pat<(v8i16 (ARMvshlu (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn))),
2126+
(v8i16 (MVE_VSHL_by_vecu16 (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)))>;
2127+
def : Pat<(v16i8 (ARMvshlu (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn))),
2128+
(v16i8 (MVE_VSHL_by_vecu8 (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)))>;
2129+
2130+
def : Pat<(v4i32 (ARMvshls (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn))),
2131+
(v4i32 (MVE_VSHL_by_vecs32 (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)))>;
2132+
def : Pat<(v8i16 (ARMvshls (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn))),
2133+
(v8i16 (MVE_VSHL_by_vecs16 (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)))>;
2134+
def : Pat<(v16i8 (ARMvshls (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn))),
2135+
(v16i8 (MVE_VSHL_by_vecs8 (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)))>;
2136+
}
2137+
21222138
class MVE_shift_with_imm<string iname, string suffix, dag oops, dag iops,
21232139
string ops, vpred_ops vpred, string cstr,
21242140
list<dag> pattern=[]>
@@ -2344,6 +2360,29 @@ def MVE_VSHL_immi32 : MVE_VSHL_imm<"i32", (ins imm0_31:$imm)> {
23442360
let Inst{21} = 0b1;
23452361
}
23462362

2363+
let Predicates = [HasMVEInt] in {
2364+
def : Pat<(v4i32 (ARMvshlImm (v4i32 MQPR:$src), imm0_31:$imm)),
2365+
(v4i32 (MVE_VSHL_immi32 (v4i32 MQPR:$src), imm0_31:$imm))>;
2366+
def : Pat<(v8i16 (ARMvshlImm (v8i16 MQPR:$src), imm0_15:$imm)),
2367+
(v8i16 (MVE_VSHL_immi16 (v8i16 MQPR:$src), imm0_15:$imm))>;
2368+
def : Pat<(v16i8 (ARMvshlImm (v16i8 MQPR:$src), imm0_7:$imm)),
2369+
(v16i8 (MVE_VSHL_immi8 (v16i8 MQPR:$src), imm0_7:$imm))>;
2370+
2371+
def : Pat<(v4i32 (ARMvshruImm (v4i32 MQPR:$src), imm0_31:$imm)),
2372+
(v4i32 (MVE_VSHR_immu32 (v4i32 MQPR:$src), imm0_31:$imm))>;
2373+
def : Pat<(v8i16 (ARMvshruImm (v8i16 MQPR:$src), imm0_15:$imm)),
2374+
(v8i16 (MVE_VSHR_immu16 (v8i16 MQPR:$src), imm0_15:$imm))>;
2375+
def : Pat<(v16i8 (ARMvshruImm (v16i8 MQPR:$src), imm0_7:$imm)),
2376+
(v16i8 (MVE_VSHR_immu8 (v16i8 MQPR:$src), imm0_7:$imm))>;
2377+
2378+
def : Pat<(v4i32 (ARMvshrsImm (v4i32 MQPR:$src), imm0_31:$imm)),
2379+
(v4i32 (MVE_VSHR_imms32 (v4i32 MQPR:$src), imm0_31:$imm))>;
2380+
def : Pat<(v8i16 (ARMvshrsImm (v8i16 MQPR:$src), imm0_15:$imm)),
2381+
(v8i16 (MVE_VSHR_imms16 (v8i16 MQPR:$src), imm0_15:$imm))>;
2382+
def : Pat<(v16i8 (ARMvshrsImm (v16i8 MQPR:$src), imm0_7:$imm)),
2383+
(v16i8 (MVE_VSHR_imms8 (v16i8 MQPR:$src), imm0_7:$imm))>;
2384+
}
2385+
23472386
// end of mve_shift instructions
23482387

23492388
// start of MVE Floating Point instructions
@@ -3353,6 +3392,22 @@ defm MVE_VRSHL_qr : MVE_VxSHL_qr_types<"vrshl", 0b0, 0b1>;
33533392
defm MVE_VQSHL_qr : MVE_VxSHL_qr_types<"vqshl", 0b1, 0b0>;
33543393
defm MVE_VQRSHL_qr : MVE_VxSHL_qr_types<"vqrshl", 0b1, 0b1>;
33553394

3395+
let Predicates = [HasMVEInt] in {
3396+
def : Pat<(v4i32 (ARMvshlu (v4i32 MQPR:$Qm), (v4i32 (ARMvdup GPR:$Rm)))),
3397+
(v4i32 (MVE_VSHL_qru32 (v4i32 MQPR:$Qm), GPR:$Rm))>;
3398+
def : Pat<(v8i16 (ARMvshlu (v8i16 MQPR:$Qm), (v8i16 (ARMvdup GPR:$Rm)))),
3399+
(v8i16 (MVE_VSHL_qru16 (v8i16 MQPR:$Qm), GPR:$Rm))>;
3400+
def : Pat<(v16i8 (ARMvshlu (v16i8 MQPR:$Qm), (v16i8 (ARMvdup GPR:$Rm)))),
3401+
(v16i8 (MVE_VSHL_qru8 (v16i8 MQPR:$Qm), GPR:$Rm))>;
3402+
3403+
def : Pat<(v4i32 (ARMvshls (v4i32 MQPR:$Qm), (v4i32 (ARMvdup GPR:$Rm)))),
3404+
(v4i32 (MVE_VSHL_qrs32 (v4i32 MQPR:$Qm), GPR:$Rm))>;
3405+
def : Pat<(v8i16 (ARMvshls (v8i16 MQPR:$Qm), (v8i16 (ARMvdup GPR:$Rm)))),
3406+
(v8i16 (MVE_VSHL_qrs16 (v8i16 MQPR:$Qm), GPR:$Rm))>;
3407+
def : Pat<(v16i8 (ARMvshls (v16i8 MQPR:$Qm), (v16i8 (ARMvdup GPR:$Rm)))),
3408+
(v16i8 (MVE_VSHL_qrs8 (v16i8 MQPR:$Qm), GPR:$Rm))>;
3409+
}
3410+
33563411
class MVE_VBRSR<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
33573412
: MVE_qDest_rSrc<iname, suffix, pattern> {
33583413

‎llvm/lib/Target/ARM/ARMInstrNEON.td

+43-55
Original file line numberDiff line numberDiff line change
@@ -493,26 +493,14 @@ def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
493493
def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
494494
def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
495495

496-
// Vector Shifts
497-
def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
498-
SDTCisSameAs<0, 2>,]>;
499-
500-
def NEONvshls : SDNode<"ARMISD::VSHLs", SDTARMVSH>;
501-
def NEONvshlu : SDNode<"ARMISD::VSHLu", SDTARMVSH>;
502-
503496
// Types for vector shift by immediates. The "SHX" version is for long and
504497
// narrow operations where the source and destination vectors have different
505498
// types. The "SHINS" version is for shift and insert operations.
506-
def SDTARMVSHIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
507-
SDTCisVT<2, i32>]>;
508499
def SDTARMVSHXIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
509500
SDTCisVT<2, i32>]>;
510501
def SDTARMVSHINSIMM : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
511502
SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
512503

513-
def NEONvshlImm : SDNode<"ARMISD::VSHLIMM", SDTARMVSHIMM>;
514-
def NEONvshrsImm : SDNode<"ARMISD::VSHRsIMM", SDTARMVSHIMM>;
515-
def NEONvshruImm : SDNode<"ARMISD::VSHRuIMM", SDTARMVSHIMM>;
516504
def NEONvshrnImm : SDNode<"ARMISD::VSHRNIMM", SDTARMVSHXIMM>;
517505

518506
def NEONvrshrsImm : SDNode<"ARMISD::VRSHRsIMM", SDTARMVSHIMM>;
@@ -4269,11 +4257,11 @@ defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
42694257
int_arm_neon_vraddhn, 1>;
42704258

42714259
let Predicates = [HasNEON] in {
4272-
def : Pat<(v8i8 (trunc (NEONvshruImm (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4260+
def : Pat<(v8i8 (trunc (ARMvshruImm (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
42734261
(VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4274-
def : Pat<(v4i16 (trunc (NEONvshruImm (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4262+
def : Pat<(v4i16 (trunc (ARMvshruImm (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
42754263
(VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4276-
def : Pat<(v2i32 (trunc (NEONvshruImm (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4264+
def : Pat<(v2i32 (trunc (ARMvshruImm (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
42774265
(VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
42784266
}
42794267

@@ -5027,11 +5015,11 @@ defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
50275015
int_arm_neon_vrsubhn, 0>;
50285016

50295017
let Predicates = [HasNEON] in {
5030-
def : Pat<(v8i8 (trunc (NEONvshruImm (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
5018+
def : Pat<(v8i8 (trunc (ARMvshruImm (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
50315019
(VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
5032-
def : Pat<(v4i16 (trunc (NEONvshruImm (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
5020+
def : Pat<(v4i16 (trunc (ARMvshruImm (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
50335021
(VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
5034-
def : Pat<(v2i32 (trunc (NEONvshruImm (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
5022+
def : Pat<(v2i32 (trunc (ARMvshruImm (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
50355023
(VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
50365024
}
50375025

@@ -5522,7 +5510,7 @@ def : Pat<(v4i32 (abs (sub (zext (v4i16 DPR:$opA)), (zext (v4i16 DPR:$opB))))),
55225510

55235511
def abd_shr :
55245512
PatFrag<(ops node:$in1, node:$in2, node:$shift),
5525-
(NEONvshrsImm (sub (zext node:$in1),
5513+
(ARMvshrsImm (sub (zext node:$in1),
55265514
(zext node:$in2)), (i32 $shift))>;
55275515

55285516
let Predicates = [HasNEON] in {
@@ -5790,56 +5778,56 @@ defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
57905778
"vshl", "u", int_arm_neon_vshiftu>;
57915779

57925780
let Predicates = [HasNEON] in {
5793-
def : Pat<(v8i8 (NEONvshls (v8i8 DPR:$Dn), (v8i8 DPR:$Dm))),
5781+
def : Pat<(v8i8 (ARMvshls (v8i8 DPR:$Dn), (v8i8 DPR:$Dm))),
57945782
(VSHLsv8i8 DPR:$Dn, DPR:$Dm)>;
5795-
def : Pat<(v4i16 (NEONvshls (v4i16 DPR:$Dn), (v4i16 DPR:$Dm))),
5783+
def : Pat<(v4i16 (ARMvshls (v4i16 DPR:$Dn), (v4i16 DPR:$Dm))),
57965784
(VSHLsv4i16 DPR:$Dn, DPR:$Dm)>;
5797-
def : Pat<(v2i32 (NEONvshls (v2i32 DPR:$Dn), (v2i32 DPR:$Dm))),
5785+
def : Pat<(v2i32 (ARMvshls (v2i32 DPR:$Dn), (v2i32 DPR:$Dm))),
57985786
(VSHLsv2i32 DPR:$Dn, DPR:$Dm)>;
5799-
def : Pat<(v1i64 (NEONvshls (v1i64 DPR:$Dn), (v1i64 DPR:$Dm))),
5787+
def : Pat<(v1i64 (ARMvshls (v1i64 DPR:$Dn), (v1i64 DPR:$Dm))),
58005788
(VSHLsv1i64 DPR:$Dn, DPR:$Dm)>;
5801-
def : Pat<(v16i8 (NEONvshls (v16i8 QPR:$Dn), (v16i8 QPR:$Dm))),
5789+
def : Pat<(v16i8 (ARMvshls (v16i8 QPR:$Dn), (v16i8 QPR:$Dm))),
58025790
(VSHLsv16i8 QPR:$Dn, QPR:$Dm)>;
5803-
def : Pat<(v8i16 (NEONvshls (v8i16 QPR:$Dn), (v8i16 QPR:$Dm))),
5791+
def : Pat<(v8i16 (ARMvshls (v8i16 QPR:$Dn), (v8i16 QPR:$Dm))),
58045792
(VSHLsv8i16 QPR:$Dn, QPR:$Dm)>;
5805-
def : Pat<(v4i32 (NEONvshls (v4i32 QPR:$Dn), (v4i32 QPR:$Dm))),
5793+
def : Pat<(v4i32 (ARMvshls (v4i32 QPR:$Dn), (v4i32 QPR:$Dm))),
58065794
(VSHLsv4i32 QPR:$Dn, QPR:$Dm)>;
5807-
def : Pat<(v2i64 (NEONvshls (v2i64 QPR:$Dn), (v2i64 QPR:$Dm))),
5795+
def : Pat<(v2i64 (ARMvshls (v2i64 QPR:$Dn), (v2i64 QPR:$Dm))),
58085796
(VSHLsv2i64 QPR:$Dn, QPR:$Dm)>;
58095797

5810-
def : Pat<(v8i8 (NEONvshlu (v8i8 DPR:$Dn), (v8i8 DPR:$Dm))),
5798+
def : Pat<(v8i8 (ARMvshlu (v8i8 DPR:$Dn), (v8i8 DPR:$Dm))),
58115799
(VSHLuv8i8 DPR:$Dn, DPR:$Dm)>;
5812-
def : Pat<(v4i16 (NEONvshlu (v4i16 DPR:$Dn), (v4i16 DPR:$Dm))),
5800+
def : Pat<(v4i16 (ARMvshlu (v4i16 DPR:$Dn), (v4i16 DPR:$Dm))),
58135801
(VSHLuv4i16 DPR:$Dn, DPR:$Dm)>;
5814-
def : Pat<(v2i32 (NEONvshlu (v2i32 DPR:$Dn), (v2i32 DPR:$Dm))),
5802+
def : Pat<(v2i32 (ARMvshlu (v2i32 DPR:$Dn), (v2i32 DPR:$Dm))),
58155803
(VSHLuv2i32 DPR:$Dn, DPR:$Dm)>;
5816-
def : Pat<(v1i64 (NEONvshlu (v1i64 DPR:$Dn), (v1i64 DPR:$Dm))),
5804+
def : Pat<(v1i64 (ARMvshlu (v1i64 DPR:$Dn), (v1i64 DPR:$Dm))),
58175805
(VSHLuv1i64 DPR:$Dn, DPR:$Dm)>;
5818-
def : Pat<(v16i8 (NEONvshlu (v16i8 QPR:$Dn), (v16i8 QPR:$Dm))),
5806+
def : Pat<(v16i8 (ARMvshlu (v16i8 QPR:$Dn), (v16i8 QPR:$Dm))),
58195807
(VSHLuv16i8 QPR:$Dn, QPR:$Dm)>;
5820-
def : Pat<(v8i16 (NEONvshlu (v8i16 QPR:$Dn), (v8i16 QPR:$Dm))),
5808+
def : Pat<(v8i16 (ARMvshlu (v8i16 QPR:$Dn), (v8i16 QPR:$Dm))),
58215809
(VSHLuv8i16 QPR:$Dn, QPR:$Dm)>;
5822-
def : Pat<(v4i32 (NEONvshlu (v4i32 QPR:$Dn), (v4i32 QPR:$Dm))),
5810+
def : Pat<(v4i32 (ARMvshlu (v4i32 QPR:$Dn), (v4i32 QPR:$Dm))),
58235811
(VSHLuv4i32 QPR:$Dn, QPR:$Dm)>;
5824-
def : Pat<(v2i64 (NEONvshlu (v2i64 QPR:$Dn), (v2i64 QPR:$Dm))),
5812+
def : Pat<(v2i64 (ARMvshlu (v2i64 QPR:$Dn), (v2i64 QPR:$Dm))),
58255813
(VSHLuv2i64 QPR:$Dn, QPR:$Dm)>;
58265814

58275815
}
58285816

58295817
// VSHL : Vector Shift Left (Immediate)
5830-
defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshlImm>;
5818+
defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", ARMvshlImm>;
58315819

58325820
// VSHR : Vector Shift Right (Immediate)
58335821
defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
5834-
NEONvshrsImm>;
5822+
ARMvshrsImm>;
58355823
defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
5836-
NEONvshruImm>;
5824+
ARMvshruImm>;
58375825

58385826
// VSHLL : Vector Shift Left Long
58395827
defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s",
5840-
PatFrag<(ops node:$LHS, node:$RHS), (NEONvshlImm (sext node:$LHS), node:$RHS)>>;
5828+
PatFrag<(ops node:$LHS, node:$RHS), (ARMvshlImm (sext node:$LHS), node:$RHS)>>;
58415829
defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u",
5842-
PatFrag<(ops node:$LHS, node:$RHS), (NEONvshlImm (zext node:$LHS), node:$RHS)>>;
5830+
PatFrag<(ops node:$LHS, node:$RHS), (ARMvshlImm (zext node:$LHS), node:$RHS)>>;
58435831

58445832
// VSHLL : Vector Shift Left Long (with maximum shift count)
58455833
class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
@@ -5858,37 +5846,37 @@ def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
58585846
v2i64, v2i32, imm32>;
58595847

58605848
let Predicates = [HasNEON] in {
5861-
def : Pat<(v8i16 (NEONvshlImm (zext (v8i8 DPR:$Rn)), (i32 8))),
5849+
def : Pat<(v8i16 (ARMvshlImm (zext (v8i8 DPR:$Rn)), (i32 8))),
58625850
(VSHLLi8 DPR:$Rn, 8)>;
5863-
def : Pat<(v4i32 (NEONvshlImm (zext (v4i16 DPR:$Rn)), (i32 16))),
5851+
def : Pat<(v4i32 (ARMvshlImm (zext (v4i16 DPR:$Rn)), (i32 16))),
58645852
(VSHLLi16 DPR:$Rn, 16)>;
5865-
def : Pat<(v2i64 (NEONvshlImm (zext (v2i32 DPR:$Rn)), (i32 32))),
5853+
def : Pat<(v2i64 (ARMvshlImm (zext (v2i32 DPR:$Rn)), (i32 32))),
58665854
(VSHLLi32 DPR:$Rn, 32)>;
5867-
def : Pat<(v8i16 (NEONvshlImm (sext (v8i8 DPR:$Rn)), (i32 8))),
5855+
def : Pat<(v8i16 (ARMvshlImm (sext (v8i8 DPR:$Rn)), (i32 8))),
58685856
(VSHLLi8 DPR:$Rn, 8)>;
5869-
def : Pat<(v4i32 (NEONvshlImm (sext (v4i16 DPR:$Rn)), (i32 16))),
5857+
def : Pat<(v4i32 (ARMvshlImm (sext (v4i16 DPR:$Rn)), (i32 16))),
58705858
(VSHLLi16 DPR:$Rn, 16)>;
5871-
def : Pat<(v2i64 (NEONvshlImm (sext (v2i32 DPR:$Rn)), (i32 32))),
5859+
def : Pat<(v2i64 (ARMvshlImm (sext (v2i32 DPR:$Rn)), (i32 32))),
58725860
(VSHLLi32 DPR:$Rn, 32)>;
5873-
def : Pat<(v8i16 (NEONvshlImm (anyext (v8i8 DPR:$Rn)), (i32 8))),
5861+
def : Pat<(v8i16 (ARMvshlImm (anyext (v8i8 DPR:$Rn)), (i32 8))),
58745862
(VSHLLi8 DPR:$Rn, 8)>;
5875-
def : Pat<(v4i32 (NEONvshlImm (anyext (v4i16 DPR:$Rn)), (i32 16))),
5863+
def : Pat<(v4i32 (ARMvshlImm (anyext (v4i16 DPR:$Rn)), (i32 16))),
58765864
(VSHLLi16 DPR:$Rn, 16)>;
5877-
def : Pat<(v2i64 (NEONvshlImm (anyext (v2i32 DPR:$Rn)), (i32 32))),
5865+
def : Pat<(v2i64 (ARMvshlImm (anyext (v2i32 DPR:$Rn)), (i32 32))),
58785866
(VSHLLi32 DPR:$Rn, 32)>;
58795867
}
58805868

58815869
// VSHRN : Vector Shift Right and Narrow
58825870
defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
58835871
PatFrag<(ops node:$Rn, node:$amt),
5884-
(trunc (NEONvshrsImm node:$Rn, node:$amt))>>;
5872+
(trunc (ARMvshrsImm node:$Rn, node:$amt))>>;
58855873

58865874
let Predicates = [HasNEON] in {
5887-
def : Pat<(v8i8 (trunc (NEONvshruImm (v8i16 QPR:$Vn), shr_imm8:$amt))),
5875+
def : Pat<(v8i8 (trunc (ARMvshruImm (v8i16 QPR:$Vn), shr_imm8:$amt))),
58885876
(VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>;
5889-
def : Pat<(v4i16 (trunc (NEONvshruImm (v4i32 QPR:$Vn), shr_imm16:$amt))),
5877+
def : Pat<(v4i16 (trunc (ARMvshruImm (v4i32 QPR:$Vn), shr_imm16:$amt))),
58905878
(VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>;
5891-
def : Pat<(v2i32 (trunc (NEONvshruImm (v2i64 QPR:$Vn), shr_imm32:$amt))),
5879+
def : Pat<(v2i32 (trunc (ARMvshruImm (v2i64 QPR:$Vn), shr_imm32:$amt))),
58925880
(VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>;
58935881
}
58945882

@@ -5952,8 +5940,8 @@ defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
59525940
NEONvqrshrnsuImm>;
59535941

59545942
// VSRA : Vector Shift Right and Accumulate
5955-
defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrsImm>;
5956-
defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshruImm>;
5943+
defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", ARMvshrsImm>;
5944+
defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", ARMvshruImm>;
59575945
// VRSRA : Vector Rounding Shift Right and Accumulate
59585946
defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrsImm>;
59595947
defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshruImm>;

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