We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 1f05b14 commit 92e38d7Copy full SHA for 92e38d7
lib/clang/libllvm/Makefile
@@ -1562,7 +1562,6 @@ SRCS_MIN+= Target/RISCV/RISCVInsertVSETVLI.cpp
1562
SRCS_MIN+= Target/RISCV/RISCVInsertWriteVXRM.cpp
1563
SRCS_MIN+= Target/RISCV/RISCVInstrInfo.cpp
1564
SRCS_MIN+= Target/RISCV/RISCVMachineFunctionInfo.cpp
1565
-SRCS_MIN+= Target/RISCV/RISCVMacroFusion.cpp
1566
SRCS_MIN+= Target/RISCV/RISCVMakeCompressible.cpp
1567
SRCS_MIN+= Target/RISCV/RISCVMergeBaseOffset.cpp
1568
SRCS_MIN+= Target/RISCV/RISCVMoveMerger.cpp
0 commit comments