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MabezDevMabezDev
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Initial asm! port in with all registers for esp32, esp32s2 (s3 not supported in llvm).
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4 files changed

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lines changed

4 files changed

+218
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lines changed

‎compiler/rustc_codegen_llvm/src/asm.rs

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -288,6 +288,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
288288
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
289289
InlineAsmArch::SpirV => {}
290290
InlineAsmArch::Wasm32 => {}
291+
InlineAsmArch::Xtensa => {}
291292
InlineAsmArch::Bpf => {}
292293
}
293294
}
@@ -594,6 +595,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
594595
InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
595596
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
596597
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r",
598+
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => "r",
599+
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => "f",
600+
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::breg) => "b",
597601
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
598602
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
599603
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
@@ -637,6 +641,7 @@ fn modifier_to_llvm(
637641
InlineAsmRegClass::Mips(_) => None,
638642
InlineAsmRegClass::Nvptx(_) => None,
639643
InlineAsmRegClass::PowerPC(_) => None,
644+
InlineAsmRegClass::Xtensa(_) => None,
640645
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
641646
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
642647
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
@@ -712,6 +717,9 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
712717
| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
713718
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
714719
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
720+
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => cx.type_i32(),
721+
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => cx.type_f32(),
722+
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::breg) => cx.type_i1(),
715723
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(),
716724
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(),
717725
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {

‎compiler/rustc_span/src/symbol.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -332,6 +332,7 @@ symbols! {
332332
braced_empty_structs,
333333
branch,
334334
breakpoint,
335+
breg,
335336
bridge,
336337
bswap,
337338
c_str,

‎compiler/rustc_target/src/asm/mod.rs

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ mod powerpc;
156156
mod riscv;
157157
mod spirv;
158158
mod wasm;
159+
mod xtensa;
159160
mod x86;
160161

161162
pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
@@ -168,6 +169,7 @@ pub use powerpc::{PowerPCInlineAsmReg, PowerPCInlineAsmRegClass};
168169
pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
169170
pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
170171
pub use wasm::{WasmInlineAsmReg, WasmInlineAsmRegClass};
172+
pub use xtensa::{XtensaInlineAsmReg, XtensaInlineAsmRegClass};
171173
pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
172174

173175
#[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)]
@@ -186,6 +188,7 @@ pub enum InlineAsmArch {
186188
PowerPC64,
187189
SpirV,
188190
Wasm32,
191+
Xtensa,
189192
Bpf,
190193
}
191194

@@ -208,6 +211,7 @@ impl FromStr for InlineAsmArch {
208211
"mips64" => Ok(Self::Mips64),
209212
"spirv" => Ok(Self::SpirV),
210213
"wasm32" => Ok(Self::Wasm32),
214+
"xtensa" => Ok(Self::Xtensa),
211215
"bpf" => Ok(Self::Bpf),
212216
_ => Err(()),
213217
}
@@ -237,6 +241,7 @@ pub enum InlineAsmReg {
237241
Mips(MipsInlineAsmReg),
238242
SpirV(SpirVInlineAsmReg),
239243
Wasm(WasmInlineAsmReg),
244+
Xtensa(XtensaInlineAsmReg),
240245
Bpf(BpfInlineAsmReg),
241246
// Placeholder for invalid register constraints for the current target
242247
Err,
@@ -252,6 +257,7 @@ impl InlineAsmReg {
252257
Self::PowerPC(r) => r.name(),
253258
Self::Hexagon(r) => r.name(),
254259
Self::Mips(r) => r.name(),
260+
Self::Xtensa(r) => r.name(),
255261
Self::Bpf(r) => r.name(),
256262
Self::Err => "<reg>",
257263
}
@@ -266,6 +272,7 @@ impl InlineAsmReg {
266272
Self::PowerPC(r) => InlineAsmRegClass::PowerPC(r.reg_class()),
267273
Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
268274
Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
275+
Self::Xtensa(r) => InlineAsmRegClass::Xtensa(r.reg_class()),
269276
Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),
270277
Self::Err => InlineAsmRegClass::Err,
271278
}
@@ -311,6 +318,9 @@ impl InlineAsmReg {
311318
InlineAsmArch::Wasm32 => {
312319
Self::Wasm(WasmInlineAsmReg::parse(arch, has_feature, target, &name)?)
313320
}
321+
InlineAsmArch::Xtensa => {
322+
Self::Xtensa(XtensaInlineAsmReg::parse(arch, has_feature, target, &name)?)
323+
}
314324
InlineAsmArch::Bpf => {
315325
Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, &name)?)
316326
}
@@ -333,6 +343,7 @@ impl InlineAsmReg {
333343
Self::PowerPC(r) => r.emit(out, arch, modifier),
334344
Self::Hexagon(r) => r.emit(out, arch, modifier),
335345
Self::Mips(r) => r.emit(out, arch, modifier),
346+
Self::Xtensa(r) => r.emit(out, arch, modifier),
336347
Self::Bpf(r) => r.emit(out, arch, modifier),
337348
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
338349
}
@@ -347,6 +358,7 @@ impl InlineAsmReg {
347358
Self::PowerPC(_) => cb(self),
348359
Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
349360
Self::Mips(_) => cb(self),
361+
Self::Xtensa(_) => cb(self),
350362
Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
351363
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
352364
}
@@ -376,6 +388,7 @@ pub enum InlineAsmRegClass {
376388
Mips(MipsInlineAsmRegClass),
377389
SpirV(SpirVInlineAsmRegClass),
378390
Wasm(WasmInlineAsmRegClass),
391+
Xtensa(XtensaInlineAsmRegClass),
379392
Bpf(BpfInlineAsmRegClass),
380393
// Placeholder for invalid register constraints for the current target
381394
Err,
@@ -394,6 +407,7 @@ impl InlineAsmRegClass {
394407
Self::Mips(r) => r.name(),
395408
Self::SpirV(r) => r.name(),
396409
Self::Wasm(r) => r.name(),
410+
Self::Xtensa(r) => r.name(),
397411
Self::Bpf(r) => r.name(),
398412
Self::Err => rustc_span::symbol::sym::reg,
399413
}
@@ -414,6 +428,7 @@ impl InlineAsmRegClass {
414428
Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
415429
Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
416430
Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm),
431+
Self::Xtensa(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Xtensa),
417432
Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf),
418433
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
419434
}
@@ -441,6 +456,7 @@ impl InlineAsmRegClass {
441456
Self::Mips(r) => r.suggest_modifier(arch, ty),
442457
Self::SpirV(r) => r.suggest_modifier(arch, ty),
443458
Self::Wasm(r) => r.suggest_modifier(arch, ty),
459+
Self::Xtensa(r) => r.suggest_modifier(arch, ty),
444460
Self::Bpf(r) => r.suggest_modifier(arch, ty),
445461
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
446462
}
@@ -464,6 +480,7 @@ impl InlineAsmRegClass {
464480
Self::Mips(r) => r.default_modifier(arch),
465481
Self::SpirV(r) => r.default_modifier(arch),
466482
Self::Wasm(r) => r.default_modifier(arch),
483+
Self::Xtensa(r) => r.default_modifier(arch),
467484
Self::Bpf(r) => r.default_modifier(arch),
468485
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
469486
}
@@ -486,6 +503,7 @@ impl InlineAsmRegClass {
486503
Self::Mips(r) => r.supported_types(arch),
487504
Self::SpirV(r) => r.supported_types(arch),
488505
Self::Wasm(r) => r.supported_types(arch),
506+
Self::Xtensa(r) => r.supported_types(arch),
489507
Self::Bpf(r) => r.supported_types(arch),
490508
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
491509
}
@@ -511,6 +529,7 @@ impl InlineAsmRegClass {
511529
}
512530
InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),
513531
InlineAsmArch::Wasm32 => Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?),
532+
InlineAsmArch::Xtensa => Self::Xtensa(XtensaInlineAsmRegClass::parse(arch, name)?),
514533
InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?),
515534
})
516535
}
@@ -529,6 +548,7 @@ impl InlineAsmRegClass {
529548
Self::Mips(r) => r.valid_modifiers(arch),
530549
Self::SpirV(r) => r.valid_modifiers(arch),
531550
Self::Wasm(r) => r.valid_modifiers(arch),
551+
Self::Xtensa(r) => r.valid_modifiers(arch),
532552
Self::Bpf(r) => r.valid_modifiers(arch),
533553
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
534554
}
@@ -699,6 +719,11 @@ pub fn allocatable_registers(
699719
wasm::fill_reg_map(arch, has_feature, target, &mut map);
700720
map
701721
}
722+
InlineAsmArch::Xtensa => {
723+
let mut map = xtensa::regclass_map();
724+
xtensa::fill_reg_map(arch, has_feature, target, &mut map);
725+
map
726+
}
702727
InlineAsmArch::Bpf => {
703728
let mut map = bpf::regclass_map();
704729
bpf::fill_reg_map(arch, has_feature, target, &mut map);

‎compiler/rustc_target/src/asm/xtensa.rs

Lines changed: 184 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,184 @@
1+
use super::{InlineAsmArch, InlineAsmType};
2+
// use crate::spec::Target;
3+
use rustc_macros::HashStable_Generic;
4+
use std::fmt;
5+
6+
def_reg_class! {
7+
Xtensa XtensaInlineAsmRegClass {
8+
reg,
9+
freg,
10+
breg,
11+
}
12+
}
13+
14+
impl XtensaInlineAsmRegClass {
15+
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
16+
&[]
17+
}
18+
19+
pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
20+
None
21+
}
22+
23+
pub fn suggest_modifier(
24+
self,
25+
_arch: InlineAsmArch,
26+
_ty: InlineAsmType,
27+
) -> Option<(char, &'static str)> {
28+
None
29+
}
30+
31+
pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
32+
None
33+
}
34+
35+
pub fn supported_types(
36+
self,
37+
_arch: InlineAsmArch,
38+
) -> &'static [(InlineAsmType, Option<&'static str>)] {
39+
match self {
40+
Self::reg | Self::breg => types! { _: I8, I16, I32; },
41+
Self::freg => types! { _: F32; },
42+
}
43+
}
44+
}
45+
46+
def_regs! {
47+
Xtensa XtensaInlineAsmReg XtensaInlineAsmRegClass {
48+
a0: reg = ["a0"],
49+
sp: reg = ["sp", "a1"],
50+
a2: reg = ["a2"],
51+
a3: reg = ["a3"],
52+
a4: reg = ["a4"],
53+
a5: reg = ["a5"],
54+
a6: reg = ["a6"],
55+
a7: reg = ["a7"],
56+
a8: reg = ["a8"],
57+
a9: reg = ["a9"],
58+
a10: reg = ["a10"],
59+
a11: reg = ["a11"],
60+
a12: reg = ["a12"],
61+
a13: reg = ["a13"],
62+
a14: reg = ["a14"],
63+
a15: reg = ["a15"],
64+
lbeg: reg = ["lbeg"],
65+
lend: reg = ["lend"],
66+
lcount: reg = ["lcount"],
67+
sar: reg = ["sar"],
68+
br: reg = ["br"],
69+
litbase: reg = ["litbase"],
70+
scompare1: reg = ["scompare1"],
71+
acclo: reg = ["acclo"],
72+
acchi: reg = ["acchi"],
73+
m0: reg = ["m0"],
74+
m1: reg = ["m1"],
75+
m2: reg = ["m2"],
76+
m3: reg = ["m3"],
77+
windowbase: reg = ["windowbase"],
78+
windowstart: reg = ["windowstart"],
79+
ibreakenable: reg = ["ibreakenable"],
80+
memctl: reg = ["memctl"],
81+
atomctl: reg = ["atomctl"],
82+
ddr: reg = ["ddr"],
83+
ibreaka0: reg = ["ibreaka0"],
84+
ibreaka1: reg = ["ibreaka1"],
85+
dbreaka0: reg = ["dbreaka0"],
86+
dbreaka1: reg = ["dbreaka1"],
87+
dbreakc0: reg = ["dbreakc0"],
88+
dbreakc1: reg = ["dbreakc1"],
89+
configid0: reg = ["configid0"],
90+
epc1: reg = ["epc1"],
91+
epc2: reg = ["epc2"],
92+
epc3: reg = ["epc3"],
93+
epc4: reg = ["epc4"],
94+
epc5: reg = ["epc5"],
95+
epc6: reg = ["epc6"],
96+
epc7: reg = ["epc7"],
97+
depc: reg = ["depc"],
98+
eps2: reg = ["eps2"],
99+
eps3: reg = ["eps3"],
100+
eps4: reg = ["eps4"],
101+
eps5: reg = ["eps5"],
102+
eps6: reg = ["eps6"],
103+
eps7: reg = ["eps7"],
104+
configid1: reg = ["configid1"],
105+
excsave1: reg = ["excsave1"],
106+
excsave2: reg = ["excsave2"],
107+
excsave3: reg = ["excsave3"],
108+
excsave4: reg = ["excsave4"],
109+
excsave5: reg = ["excsave5"],
110+
excsave6: reg = ["excsave6"],
111+
excsave7: reg = ["excsave7"],
112+
cpenable: reg = ["cpenable"],
113+
interrupt: reg = ["interrupt"],
114+
intclear: reg = ["intclear"],
115+
intenable: reg = ["intenable"],
116+
ps: reg = ["ps"],
117+
vecbase: reg = ["vecbase"],
118+
exccause: reg = ["exccause"],
119+
debugcause: reg = ["debugcause"],
120+
ccount: reg = ["ccount"],
121+
prid: reg = ["prid"],
122+
icount: reg = ["icount"],
123+
icountlevel: reg = ["icountlevel"],
124+
excvaddr: reg = ["excvaddr"],
125+
ccompare0: reg = ["ccompare0"],
126+
ccompare1: reg = ["ccompare1"],
127+
ccompare2: reg = ["ccompare2"],
128+
misc0: reg = ["misc0"],
129+
misc1: reg = ["misc1"],
130+
misc2: reg = ["misc2"],
131+
misc3: reg = ["misc3"],
132+
gpio_out: reg = ["gpio_out"],
133+
expstate: reg = ["expstate"],
134+
threadptr: reg = ["threadptr"],
135+
fcr: reg = ["fcr"],
136+
fsr: reg = ["fsr"],
137+
f64r_lo: reg = ["f64r_lo"],
138+
f64r_hi: reg = ["f64r_hi"],
139+
f64s: reg = ["f64s"],
140+
f0: freg = ["f0"],
141+
f1: freg = ["f1"],
142+
f2: freg = ["f2"],
143+
f3: freg = ["f3"],
144+
f4: freg = ["f4"],
145+
f5: freg = ["f5"],
146+
f6: freg = ["f6"],
147+
f7: freg = ["f7"],
148+
f8: freg = ["f8"],
149+
f9: freg = ["f9"],
150+
f10: freg = ["f10"],
151+
f11: freg = ["f11"],
152+
f12: freg = ["f12"],
153+
f13: freg = ["f13"],
154+
f14: freg = ["f14"],
155+
f15: freg = ["f15"],
156+
b0: breg = ["b0"],
157+
b1: breg = ["b1"],
158+
b2: breg = ["b2"],
159+
b3: breg = ["b3"],
160+
b4: breg = ["b4"],
161+
b5: breg = ["b5"],
162+
b6: breg = ["b6"],
163+
b7: breg = ["b7"],
164+
b8: breg = ["b8"],
165+
b9: breg = ["b9"],
166+
b10: breg = ["b10"],
167+
b11: breg = ["b11"],
168+
b12: breg = ["b12"],
169+
b13: breg = ["b13"],
170+
b14: breg = ["b14"],
171+
b15: breg = ["b15"],
172+
}
173+
}
174+
175+
impl XtensaInlineAsmReg {
176+
pub fn emit(
177+
self,
178+
out: &mut dyn fmt::Write,
179+
_arch: InlineAsmArch,
180+
_modifier: Option<char>,
181+
) -> fmt::Result {
182+
out.write_str(self.name())
183+
}
184+
}

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