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[GlobalIsel][AArch64] more legal icmps (llvm#78239)
In llvm#78181 the godbolt (https://llvm.godbolt.org/z/vMsnxMf1v) crashed with GlobalIsel. LLVM ERROR: unable to legalize instruction: %90:_(<3 x s32>) = G_ICMP intpred(uge), %15:_(<3 x s32>), %0:_ (in function: vec3_i32)
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6 files changed

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‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5314,6 +5314,17 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
53145314
Observer.changedInstr(MI);
53155315
return Legalized;
53165316
}
5317+
case TargetOpcode::G_ICMP: {
5318+
// TODO: the symmetric MoreTy works for targets like, e.g. NEON.
5319+
// For targets, like e.g. MVE, the result is a predicated vector (i1).
5320+
// This will need some refactoring.
5321+
Observer.changingInstr(MI);
5322+
moreElementsVectorSrc(MI, MoreTy, 2);
5323+
moreElementsVectorSrc(MI, MoreTy, 3);
5324+
moreElementsVectorDst(MI, MoreTy, 0);
5325+
Observer.changedInstr(MI);
5326+
return Legalized;
5327+
}
53175328
default:
53185329
return UnableToLegalize;
53195330
}

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -495,6 +495,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
495495
})
496496
.clampScalar(0, MinFPScalar, s128);
497497

498+
// FIXME: fix moreElementsToNextPow2
498499
getActionDefinitionsBuilder(G_ICMP)
499500
.legalFor({{s32, s32},
500501
{s32, s64},
@@ -524,7 +525,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
524525
.minScalarOrEltIf(
525526
[=](const LegalityQuery &Query) { return Query.Types[1] == v2p0; }, 0,
526527
s64)
527-
.clampNumElements(0, v2s32, v4s32);
528+
.moreElementsToNextPow2(0)
529+
.clampNumElements(0, v8s8, v16s8)
530+
.clampNumElements(0, v4s16, v8s16)
531+
.clampNumElements(0, v2s32, v4s32)
532+
.clampNumElements(0, v2s64, v2s64);
528533

529534
getActionDefinitionsBuilder(G_FCMP)
530535
// If we don't have full FP16 support, then scalarize the elements of
@@ -863,6 +868,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
863868
},
864869
0, s8)
865870
.minScalarOrElt(0, s8) // Worst case, we need at least s8.
871+
.moreElementsToNextPow2(1)
866872
.clampMaxNumElements(1, s64, 2)
867873
.clampMaxNumElements(1, s32, 4)
868874
.clampMaxNumElements(1, s16, 8)

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

Lines changed: 205 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -330,3 +330,208 @@ body: |
330330
successors:
331331
bb.3:
332332
RET_ReallyLR
333+
...
334+
---
335+
name: test_3xs32_eq_pr_78181
336+
tracksRegLiveness: true
337+
body: |
338+
bb.1:
339+
liveins: $x0
340+
; CHECK-LABEL: name: test_3xs32_eq_pr_78181
341+
; CHECK: liveins: $x0
342+
; CHECK-NEXT: {{ $}}
343+
; CHECK-NEXT: %const:_(s32) = G_IMPLICIT_DEF
344+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
345+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
346+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]]
347+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
348+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ICMP]](<4 x s32>), [[C]](s64)
349+
; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
350+
; CHECK-NEXT: RET_ReallyLR
351+
%const:_(s32) = G_IMPLICIT_DEF
352+
%rhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32)
353+
%lhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32)
354+
%cmp:_(<3 x s32>) = G_ICMP intpred(eq), %lhs(<3 x s32>), %rhs
355+
%1:_(s32) = G_CONSTANT i32 1
356+
%2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s32>), %1(s32)
357+
$w0 = COPY %2(s32)
358+
RET_ReallyLR
359+
...
360+
---
361+
name: test_3xs16_eq_pr_78181
362+
tracksRegLiveness: true
363+
body: |
364+
bb.1:
365+
liveins: $x0
366+
; CHECK-LABEL: name: test_3xs16_eq_pr_78181
367+
; CHECK: liveins: $x0
368+
; CHECK-NEXT: {{ $}}
369+
; CHECK-NEXT: %const:_(s16) = G_IMPLICIT_DEF
370+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16)
371+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16)
372+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<4 x s16>), [[BUILD_VECTOR1]]
373+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[ICMP]](<4 x s16>)
374+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
375+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
376+
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
377+
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
378+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
379+
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[DEF]](s32)
380+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR2]](<4 x s32>), [[C]](s64)
381+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
382+
; CHECK-NEXT: %zext:_(s32) = G_AND [[EVEC]], [[C1]]
383+
; CHECK-NEXT: $w0 = COPY %zext(s32)
384+
; CHECK-NEXT: RET_ReallyLR
385+
%const:_(s16) = G_IMPLICIT_DEF
386+
%rhs:_(<3 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16)
387+
%lhs:_(<3 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16)
388+
%cmp:_(<3 x s16>) = G_ICMP intpred(eq), %lhs(<3 x s16>), %rhs
389+
%1:_(s32) = G_CONSTANT i32 1
390+
%2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s16>), %1(s32)
391+
%zext:_(s32) = G_ZEXT %2(s16)
392+
$w0 = COPY %zext(s32)
393+
RET_ReallyLR
394+
...
395+
---
396+
name: test_3xs8_eq_pr_78181
397+
tracksRegLiveness: true
398+
body: |
399+
bb.1:
400+
liveins: $x0
401+
; CHECK-LABEL: name: test_3xs8_eq_pr_78181
402+
; CHECK: liveins: $x0
403+
; CHECK-NEXT: {{ $}}
404+
; CHECK-NEXT: %const:_(s8) = G_IMPLICIT_DEF
405+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
406+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
407+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<8 x s8>), [[BUILD_VECTOR1]]
408+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[ICMP]](<8 x s8>)
409+
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UV]](<4 x s8>)
410+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
411+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
412+
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
413+
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
414+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
415+
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[DEF]](s32)
416+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR2]](<4 x s32>), [[C]](s64)
417+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
418+
; CHECK-NEXT: %zext:_(s32) = G_AND [[EVEC]], [[C1]]
419+
; CHECK-NEXT: $w0 = COPY %zext(s32)
420+
; CHECK-NEXT: RET_ReallyLR
421+
%const:_(s8) = G_IMPLICIT_DEF
422+
%rhs:_(<3 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8)
423+
%lhs:_(<3 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8)
424+
%cmp:_(<3 x s8>) = G_ICMP intpred(eq), %lhs(<3 x s8>), %rhs
425+
%1:_(s32) = G_CONSTANT i32 1
426+
%2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s8>), %1(s32)
427+
%zext:_(s32) = G_ZEXT %2(s8)
428+
$w0 = COPY %zext(s32)
429+
RET_ReallyLR
430+
...
431+
---
432+
name: test_3xs64_eq_clamp
433+
tracksRegLiveness: true
434+
body: |
435+
bb.1:
436+
liveins: $x0
437+
; CHECK-LABEL: name: test_3xs64_eq_clamp
438+
; CHECK: liveins: $x0
439+
; CHECK-NEXT: {{ $}}
440+
; CHECK-NEXT: %const:_(s64) = G_IMPLICIT_DEF
441+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64)
442+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64)
443+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<2 x s64>), [[BUILD_VECTOR1]]
444+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
445+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[ICMP]](<2 x s64>), [[C]](s64)
446+
; CHECK-NEXT: $x0 = COPY [[EVEC]](s64)
447+
; CHECK-NEXT: RET_ReallyLR
448+
%const:_(s64) = G_IMPLICIT_DEF
449+
%rhs:_(<3 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64), %const(s64)
450+
%lhs:_(<3 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64), %const(s64)
451+
%cmp:_(<3 x s64>) = G_ICMP intpred(eq), %lhs(<3 x s64>), %rhs
452+
%1:_(s32) = G_CONSTANT i32 1
453+
%2:_(s64) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s64>), %1(s32)
454+
$x0 = COPY %2(s64)
455+
RET_ReallyLR
456+
...
457+
---
458+
name: test_5xs32_eq_clamp
459+
tracksRegLiveness: true
460+
body: |
461+
bb.1:
462+
liveins: $x0
463+
; CHECK-LABEL: name: test_5xs32_eq_clamp
464+
; CHECK: liveins: $x0
465+
; CHECK-NEXT: {{ $}}
466+
; CHECK-NEXT: %const:_(s32) = G_IMPLICIT_DEF
467+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
468+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
469+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]]
470+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
471+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ICMP]](<4 x s32>), [[C]](s64)
472+
; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
473+
; CHECK-NEXT: RET_ReallyLR
474+
%const:_(s32) = G_IMPLICIT_DEF
475+
%rhs:_(<5 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32), %const(s32)
476+
%lhs:_(<5 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32), %const(s32)
477+
%cmp:_(<5 x s32>) = G_ICMP intpred(eq), %lhs(<5 x s32>), %rhs
478+
%1:_(s32) = G_CONSTANT i32 1
479+
%2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<5 x s32>), %1(s32)
480+
$w0 = COPY %2(s32)
481+
RET_ReallyLR
482+
...
483+
---
484+
name: test_7xs16_eq_clamp
485+
tracksRegLiveness: true
486+
body: |
487+
bb.1:
488+
liveins: $x0
489+
; CHECK-LABEL: name: test_7xs16_eq_clamp
490+
; CHECK: liveins: $x0
491+
; CHECK-NEXT: {{ $}}
492+
; CHECK-NEXT: %const:_(s16) = G_IMPLICIT_DEF
493+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16)
494+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16)
495+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<8 x s16>), [[BUILD_VECTOR1]]
496+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
497+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[ICMP]](<8 x s16>), [[C]](s64)
498+
; CHECK-NEXT: %zext:_(s32) = G_ZEXT [[EVEC]](s16)
499+
; CHECK-NEXT: $w0 = COPY %zext(s32)
500+
; CHECK-NEXT: RET_ReallyLR
501+
%const:_(s16) = G_IMPLICIT_DEF
502+
%rhs:_(<7 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16)
503+
%lhs:_(<7 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16)
504+
%cmp:_(<7 x s16>) = G_ICMP intpred(eq), %lhs(<7 x s16>), %rhs
505+
%1:_(s32) = G_CONSTANT i32 1
506+
%2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<7 x s16>), %1(s32)
507+
%zext:_(s32) = G_ZEXT %2(s16)
508+
$w0 = COPY %zext(s32)
509+
RET_ReallyLR
510+
...
511+
---
512+
name: test_9xs8_eq_clamp
513+
tracksRegLiveness: true
514+
body: |
515+
bb.1:
516+
liveins: $x0
517+
; CHECK-LABEL: name: test_9xs8_eq_clamp
518+
; CHECK: liveins: $x0
519+
; CHECK-NEXT: {{ $}}
520+
; CHECK-NEXT: %const:_(s8) = G_IMPLICIT_DEF
521+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
522+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
523+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<16 x s8>), [[BUILD_VECTOR1]]
524+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
525+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[ICMP]](<16 x s8>), [[C]](s64)
526+
; CHECK-NEXT: %zext:_(s32) = G_ZEXT [[EVEC]](s8)
527+
; CHECK-NEXT: $w0 = COPY %zext(s32)
528+
; CHECK-NEXT: RET_ReallyLR
529+
%const:_(s8) = G_IMPLICIT_DEF
530+
%rhs:_(<9 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
531+
%lhs:_(<9 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
532+
%cmp:_(<9 x s8>) = G_ICMP intpred(eq), %lhs(<9 x s8>), %rhs
533+
%1:_(s32) = G_CONSTANT i32 1
534+
%2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<9 x s8>), %1(s32)
535+
%zext:_(s32) = G_ZEXT %2(s8)
536+
$w0 = COPY %zext(s32)
537+
RET_ReallyLR

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -316,26 +316,14 @@ body: |
316316
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[DEF]](s32)
317317
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[DEF]](s32)
318318
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]], shufflemask(0, 1, 5, 6)
319-
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[SHUF]](<4 x s32>)
320-
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s32>), [[UV3:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[SHUF]](<4 x s32>)
321-
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<2 x s32>), [[UV5:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[SHUF]](<4 x s32>)
322-
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(<2 x s32>), [[UV7:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[SHUF]](<4 x s32>)
323-
; CHECK-NEXT: [[UV8:%[0-9]+]]:_(<2 x s32>), [[UV9:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[SHUF]](<4 x s32>)
324-
; CHECK-NEXT: [[UV10:%[0-9]+]]:_(<2 x s32>), [[UV11:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[SHUF]](<4 x s32>)
325-
; CHECK-NEXT: [[UV12:%[0-9]+]]:_(<2 x s32>), [[UV13:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[SHUF]](<4 x s32>)
326-
; CHECK-NEXT: [[UV14:%[0-9]+]]:_(<2 x s32>), [[UV15:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[SHUF]](<4 x s32>)
327319
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
328-
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[UV]](<2 x s32>), [[UV3]](<2 x s32>)
329-
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[CONCAT_VECTORS]](<4 x s32>), [[C]](s64)
320+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](s64)
330321
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
331-
; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[UV4]](<2 x s32>), [[UV7]](<2 x s32>)
332-
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[CONCAT_VECTORS1]](<4 x s32>), [[C1]](s64)
322+
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C1]](s64)
333323
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
334-
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[UV8]](<2 x s32>), [[UV11]](<2 x s32>)
335-
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[CONCAT_VECTORS2]](<4 x s32>), [[C2]](s64)
324+
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C2]](s64)
336325
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
337-
; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[UV12]](<2 x s32>), [[UV15]](<2 x s32>)
338-
; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[CONCAT_VECTORS3]](<4 x s32>), [[C3]](s64)
326+
; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C3]](s64)
339327
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[EVEC]](s32), [[EVEC1]](s32), [[EVEC2]](s32), [[EVEC3]](s32)
340328
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR2]](<4 x s32>)
341329
; CHECK-NEXT: RET_ReallyLR implicit $q0

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