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[VPlan] Use VPInstruction for uniform binops.
Use VPInstruction instead of VPReplicate recipe for uniform binops. This is a step towards breaking up VPReplicateRecipe. Using the general VPInstruction has the additional benefit that we can now apply a number of simplifications directly. Depends on llvm#140623.
1 parent 9c1a5df commit b6473fe

11 files changed

+96
-76
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8453,12 +8453,20 @@ VPRecipeBuilder::handleReplication(Instruction *I, ArrayRef<VPValue *> Operands,
84538453
assert((Range.Start.isScalar() || !IsUniform || !IsPredicated ||
84548454
(Range.Start.isScalable() && isa<IntrinsicInst>(I))) &&
84558455
"Should not predicate a uniform recipe");
8456-
if (IsUniform && Instruction::isCast(I->getOpcode())) {
8457-
auto *Recipe = new VPInstructionWithType(I->getOpcode(), Operands,
8458-
I->getType(), VPIRFlags(*I),
8459-
I->getDebugLoc(), I->getName());
8460-
Recipe->setUnderlyingValue(I);
8461-
return Recipe;
8456+
if (IsUniform && !IsPredicated) {
8457+
VPInstruction *VPI = nullptr;
8458+
if (Instruction::isCast(I->getOpcode())) {
8459+
VPI = new VPInstructionWithType(I->getOpcode(), Operands, I->getType(),
8460+
VPIRFlags(*I), I->getDebugLoc(),
8461+
I->getName());
8462+
} else if (Instruction::isBinaryOp(I->getOpcode())) {
8463+
VPI = new VPInstruction(I->getOpcode(), Operands, VPIRFlags(*I),
8464+
I->getDebugLoc(), I->getName(), true);
8465+
}
8466+
if (VPI) {
8467+
VPI->setUnderlyingValue(I);
8468+
return VPI;
8469+
}
84628470
}
84638471
auto *Recipe = new VPReplicateRecipe(I, Operands, IsUniform, BlockInMask,
84648472
VPIRMetadata(*I, LVer));

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1597,12 +1597,13 @@ bool VPIRFlags::flagsValidForOpcode(unsigned Opcode) const {
15971597
switch (OpType) {
15981598
case OperationType::OverflowingBinOp:
15991599
return Opcode == Instruction::Add || Opcode == Instruction::Sub ||
1600-
Opcode == Instruction::Mul ||
1600+
Opcode == Instruction::Mul || Opcode == Instruction::Shl ||
16011601
Opcode == VPInstruction::VPInstruction::CanonicalIVIncrementForPart;
16021602
case OperationType::DisjointOp:
16031603
return Opcode == Instruction::Or;
16041604
case OperationType::PossiblyExactOp:
1605-
return Opcode == Instruction::AShr;
1605+
return Opcode == Instruction::AShr || Opcode == Instruction::LShr ||
1606+
Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
16061607
case OperationType::GEPOp:
16071608
return Opcode == Instruction::GetElementPtr ||
16081609
Opcode == VPInstruction::PtrAdd;

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,10 @@ static bool sinkScalarOperands(VPlan &Plan) {
154154
if (auto *RepR = dyn_cast<VPReplicateRecipe>(SinkCandidate)) {
155155
if (!ScalarVFOnly && RepR->isSingleScalar())
156156
continue;
157+
} else if (auto *RepR = dyn_cast<VPInstruction>(SinkCandidate)) {
158+
if ((!ScalarVFOnly && RepR->isSingleScalar()) ||
159+
!RepR->getUnderlyingValue())
160+
continue;
157161
} else if (!isa<VPScalarIVStepsRecipe>(SinkCandidate))
158162
continue;
159163

@@ -196,6 +200,15 @@ static bool sinkScalarOperands(VPlan &Plan) {
196200
SinkCandidate->replaceUsesWithIf(Clone, [SinkTo](VPUser &U, unsigned) {
197201
return cast<VPRecipeBase>(&U)->getParent() != SinkTo;
198202
});
203+
} else {
204+
if (auto *VPI = dyn_cast<VPInstruction>(SinkCandidate)) {
205+
auto *OldCand = SinkCandidate;
206+
SinkCandidate = new VPReplicateRecipe(VPI->getUnderlyingInstr(),
207+
SinkCandidate->operands(), true,
208+
nullptr /*Mask*/);
209+
SinkCandidate->insertBefore(OldCand);
210+
OldCand->replaceAllUsesWith(SinkCandidate);
211+
}
199212
}
200213
SinkCandidate->moveBefore(*SinkTo, SinkTo->getFirstNonPhi());
201214
for (VPValue *Op : SinkCandidate->operands())

‎llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ target triple = "aarch64-unknown-linux-gnu"
3232
; CHECK-NEXT: SINGLE-SCALAR [[EXT_IDX:.*]] = zext [[IDX]]
3333
; CHECK-NEXT: CLONE [[GEP_BUCKET:.*]] = getelementptr inbounds ir<%buckets>, [[EXT_IDX]]
3434
; CHECK-NEXT: CLONE [[HISTVAL:.*]] = load [[GEP_BUCKET]]
35-
; CHECK-NEXT: CLONE [[UPDATE:.*]] = add nsw [[HISTVAL]], ir<1>
35+
; CHECK-NEXT: SINGLE-SCALAR [[UPDATE:.*]] = add nsw [[HISTVAL]], ir<1>
3636
; CHECK-NEXT: CLONE store [[UPDATE]], [[GEP_BUCKET]]
3737
; CHECK-NEXT: EMIT [[IV_NEXT]] = add nuw [[IV]], [[VFxUF]]
3838
; CHECK-NEXT: EMIT branch-on-count [[IV_NEXT]], [[VTC]]

‎llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ define void @safe_dep(ptr %p) {
9494
; CHECK-NEXT: CLONE ir<%a1> = getelementptr ir<%p>, vp<[[STEPS]]>
9595
; CHECK-NEXT: vp<[[VPTR1:%.+]]> = vector-pointer ir<%a1>
9696
; CHECK-NEXT: WIDEN ir<%v> = load vp<[[VPTR1]]>
97-
; CHECK-NEXT: CLONE ir<%offset> = add vp<[[STEPS]]>, ir<100>
97+
; CHECK-NEXT: SINGLE-SCALAR ir<%offset> = add vp<[[STEPS]]>, ir<100>
9898
; CHECK-NEXT: CLONE ir<%a2> = getelementptr ir<%p>, ir<%offset>
9999
; CHECK-NEXT: vp<[[VPTR2:%.+]]> = vector-pointer ir<%a2>
100100
; CHECK-NEXT: WIDEN store vp<[[VPTR2]]>, ir<%v>

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
7474
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
7575
; CHECK-NEXT: vp<[[DEV_IV:%.+]]> = DERIVED-IV ir<%n> + vp<[[CAN_IV]]> * ir<-1>
7676
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[DEV_IV]]>, ir<-1>
77-
; CHECK-NEXT: CLONE ir<%i.0> = add nsw vp<[[STEPS]]>, ir<-1>
77+
; CHECK-NEXT: SINGLE-SCALAR ir<%i.0> = add nsw vp<[[STEPS]]>, ir<-1>
7878
; CHECK-NEXT: SINGLE-SCALAR ir<%idxprom> = zext ir<%i.0>
7979
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%B>, ir<%idxprom>
8080
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-end-pointer inbounds ir<%arrayidx>, vp<[[VF]]>
@@ -198,7 +198,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
198198
; CHECK-NEXT: vector.body:
199199
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = phi [ ir<0>, ir-bb<vector.ph> ], [ vp<[[CAN_IV_NEXT:%.+]]>, vector.body ]
200200
; CHECK-NEXT: vp<[[DEV_IV:%.+]]> = DERIVED-IV ir<%n> + vp<[[CAN_IV]]> * ir<-1>
201-
; CHECK-NEXT: CLONE ir<%i.0> = add nsw vp<[[DEV_IV]]>, ir<-1>
201+
; CHECK-NEXT: SINGLE-SCALAR ir<%i.0> = add nsw vp<[[DEV_IV]]>, ir<-1>
202202
; CHECK-NEXT: SINGLE-SCALAR ir<%idxprom> = zext ir<%i.0>
203203
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%B>, ir<%idxprom>
204204
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-end-pointer inbounds ir<%arrayidx>, ir<[[VF]]>
@@ -322,7 +322,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
322322
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
323323
; CHECK-NEXT: vp<[[DEV_IV:%.+]]> = DERIVED-IV ir<%n> + vp<[[CAN_IV]]> * ir<-1>
324324
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[DEV_IV]]>, ir<-1>
325-
; CHECK-NEXT: CLONE ir<%i.0> = add nsw vp<[[STEPS]]>, ir<-1>
325+
; CHECK-NEXT: SINGLE-SCALAR ir<%i.0> = add nsw vp<[[STEPS]]>, ir<-1>
326326
; CHECK-NEXT: SINGLE-SCALAR ir<%idxprom> = zext ir<%i.0>
327327
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%B>, ir<%idxprom>
328328
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-end-pointer inbounds ir<%arrayidx>, vp<[[VF]]>
@@ -446,7 +446,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
446446
; CHECK-NEXT: vector.body:
447447
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = phi [ ir<0>, ir-bb<vector.ph> ], [ vp<[[CAN_IV_NEXT:%.+]]>, vector.body ]
448448
; CHECK-NEXT: vp<[[DEV_IV:%.+]]> = DERIVED-IV ir<%n> + vp<[[CAN_IV]]> * ir<-1>
449-
; CHECK-NEXT: CLONE ir<%i.0> = add nsw vp<[[DEV_IV]]>, ir<-1>
449+
; CHECK-NEXT: SINGLE-SCALAR ir<%i.0> = add nsw vp<[[DEV_IV]]>, ir<-1>
450450
; CHECK-NEXT: SINGLE-SCALAR ir<%idxprom> = zext ir<%i.0>
451451
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%B>, ir<%idxprom>
452452
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-end-pointer inbounds ir<%arrayidx>, ir<[[VF]]>

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ define void @safe_dep(ptr %p) {
112112
; CHECK-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr ir<%p>, vp<[[ST]]>
113113
; CHECK-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer ir<[[GEP1]]>
114114
; CHECK-NEXT: WIDEN ir<[[V:%.+]]> = load vp<[[PTR1]]>
115-
; CHECK-NEXT: CLONE ir<[[OFFSET:.+]]> = add vp<[[ST]]>, ir<100>
115+
; CHECK-NEXT: SINGLE-SCALAR ir<[[OFFSET:.+]]> = add vp<[[ST]]>, ir<100>
116116
; CHECK-NEXT: CLONE ir<[[GEP2:%.+]]> = getelementptr ir<%p>, ir<[[OFFSET]]>
117117
; CHECK-NEXT: vp<[[PTR2:%[0-9]+]]> = vector-pointer ir<[[GEP2]]>
118118
; CHECK-NEXT: WIDEN store vp<[[PTR2]]>, ir<[[V]]>

‎llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll

Lines changed: 43 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -17,55 +17,55 @@ define void @test_pr59090(ptr %l_out, ptr noalias %b) #0 {
1717
; CHECK-NEXT: [[VEC_IV:%.*]] = add <8 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
1818
; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <8 x i64> [[VEC_IV]], splat (i64 10000)
1919
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[INDEX]], 6
20-
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[B:%.*]], align 1, !llvm.access.group [[ACC_GRP0:![0-9]+]]
20+
; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[B:%.*]], align 1, !llvm.access.group [[ACC_GRP0:![0-9]+]]
2121
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[TMP1]], i32 0
2222
; CHECK-NEXT: br i1 [[TMP4]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
2323
; CHECK: pred.store.if:
24-
; CHECK-NEXT: store i8 [[TMP3]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
24+
; CHECK-NEXT: store i8 [[TMP10]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
2525
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
2626
; CHECK: pred.store.continue:
27-
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i1> [[TMP1]], i32 1
28-
; CHECK-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]]
29-
; CHECK: pred.store.if1:
30-
; CHECK-NEXT: store i8 [[TMP3]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
31-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]]
32-
; CHECK: pred.store.continue2:
33-
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i1> [[TMP1]], i32 2
34-
; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]
35-
; CHECK: pred.store.if3:
36-
; CHECK-NEXT: store i8 [[TMP3]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
37-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]
38-
; CHECK: pred.store.continue4:
39-
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i1> [[TMP1]], i32 3
40-
; CHECK-NEXT: br i1 [[TMP7]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
41-
; CHECK: pred.store.if5:
42-
; CHECK-NEXT: store i8 [[TMP3]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
43-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
44-
; CHECK: pred.store.continue6:
45-
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i1> [[TMP1]], i32 4
46-
; CHECK-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
47-
; CHECK: pred.store.if7:
48-
; CHECK-NEXT: store i8 [[TMP3]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
49-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
50-
; CHECK: pred.store.continue8:
51-
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i1> [[TMP1]], i32 5
52-
; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10:%.*]]
53-
; CHECK: pred.store.if9:
54-
; CHECK-NEXT: store i8 [[TMP3]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
55-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE10]]
56-
; CHECK: pred.store.continue10:
57-
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i1> [[TMP1]], i32 6
58-
; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12:%.*]]
59-
; CHECK: pred.store.if11:
60-
; CHECK-NEXT: store i8 [[TMP3]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
61-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE12]]
62-
; CHECK: pred.store.continue12:
63-
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i1> [[TMP1]], i32 7
64-
; CHECK-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF13:%.*]], label [[PRED_STORE_CONTINUE14]]
65-
; CHECK: pred.store.if13:
66-
; CHECK-NEXT: store i8 [[TMP3]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
27+
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[TMP1]], i32 1
28+
; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3:%.*]]
29+
; CHECK: pred.store.if2:
30+
; CHECK-NEXT: store i8 [[TMP10]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
31+
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE3]]
32+
; CHECK: pred.store.continue3:
33+
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i1> [[TMP1]], i32 2
34+
; CHECK-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]]
35+
; CHECK: pred.store.if4:
36+
; CHECK-NEXT: store i8 [[TMP10]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
37+
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE5]]
38+
; CHECK: pred.store.continue5:
39+
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i1> [[TMP1]], i32 3
40+
; CHECK-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7:%.*]]
41+
; CHECK: pred.store.if6:
42+
; CHECK-NEXT: store i8 [[TMP10]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
43+
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE7]]
44+
; CHECK: pred.store.continue7:
45+
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i1> [[TMP1]], i32 4
46+
; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_STORE_IF8:%.*]], label [[PRED_STORE_CONTINUE9:%.*]]
47+
; CHECK: pred.store.if8:
48+
; CHECK-NEXT: store i8 [[TMP10]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
49+
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE9]]
50+
; CHECK: pred.store.continue9:
51+
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i1> [[TMP1]], i32 5
52+
; CHECK-NEXT: br i1 [[TMP7]], label [[PRED_STORE_IF10:%.*]], label [[PRED_STORE_CONTINUE11:%.*]]
53+
; CHECK: pred.store.if10:
54+
; CHECK-NEXT: store i8 [[TMP10]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
55+
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE11]]
56+
; CHECK: pred.store.continue11:
57+
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i1> [[TMP1]], i32 6
58+
; CHECK-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF12:%.*]], label [[PRED_STORE_CONTINUE13:%.*]]
59+
; CHECK: pred.store.if12:
60+
; CHECK-NEXT: store i8 [[TMP10]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
61+
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE13]]
62+
; CHECK: pred.store.continue13:
63+
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i1> [[TMP1]], i32 7
64+
; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF14:%.*]], label [[PRED_STORE_CONTINUE14]]
65+
; CHECK: pred.store.if14:
66+
; CHECK-NEXT: store i8 [[TMP10]], ptr [[B]], align 1, !llvm.access.group [[ACC_GRP0]]
6767
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE14]]
68-
; CHECK: pred.store.continue14:
68+
; CHECK: pred.store.continue15:
6969
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[L_OUT:%.*]], i64 [[TMP2]]
7070
; CHECK-NEXT: [[INTERLEAVED_MASK:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <48 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
7171
; CHECK-NEXT: [[TMP15:%.*]] = and <48 x i1> [[INTERLEAVED_MASK]], <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false>

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