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AMDGPU: Replace tests using undef in shufflevector with poison (llvm#130899)
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ define void @value_finder_bug(ptr addrspace(5) %store_ptr, ptr addrspace(4) %ptr
1212
; GFX10-NEXT: s_setpc_b64 s[30:31]
1313
%vec = load <4 x float>, ptr addrspace(4) %ptr, align 4
1414
%vec.3 = extractelement <4 x float> %vec, i32 3
15-
%shuffle = shufflevector <4 x float> %vec, <4 x float> undef, <2 x i32> <i32 2, i32 undef>
15+
%shuffle = shufflevector <4 x float> %vec, <4 x float> poison, <2 x i32> <i32 2, i32 poison>
1616
%new_vec = insertelement <2 x float> %shuffle, float %vec.3, i32 1
1717
store <2 x float> %new_vec, ptr addrspace(5) %store_ptr, align 8
1818
ret void

‎llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

Lines changed: 40 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -870,10 +870,10 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
870870
; GFX11-NEXT: s_setpc_b64 s[30:31]
871871
entry:
872872
%insert = insertelement <8 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0>, double %val, i32 %idx
873-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
874-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
875-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
876-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
873+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
874+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
875+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
876+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
877877
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
878878
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
879879
store volatile <2 x double> %vec.2, ptr addrspace(1) undef
@@ -1081,10 +1081,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
10811081
; GFX11-NEXT: s_endpgm
10821082
entry:
10831083
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
1084-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
1085-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
1086-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
1087-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
1084+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
1085+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
1086+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
1087+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
10881088
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
10891089
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
10901090
store volatile <2 x double> %vec.2, ptr addrspace(1) undef
@@ -1229,10 +1229,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_s(<8 x double> inreg %vec, do
12291229
; GFX11-NEXT: s_endpgm
12301230
entry:
12311231
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
1232-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
1233-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
1234-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
1235-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
1232+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
1233+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
1234+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
1235+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
12361236
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
12371237
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
12381238
store volatile <2 x double> %vec.2, ptr addrspace(1) undef
@@ -1289,10 +1289,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_s(<8 x double> %vec, double i
12891289
; GFX11-NEXT: s_endpgm
12901290
entry:
12911291
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
1292-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
1293-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
1294-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
1295-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
1292+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
1293+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
1294+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
1295+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
12961296
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
12971297
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
12981298
store volatile <2 x double> %vec.2, ptr addrspace(1) undef
@@ -1494,10 +1494,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
14941494
; GFX11-NEXT: s_endpgm
14951495
entry:
14961496
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
1497-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
1498-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
1499-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
1500-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
1497+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
1498+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
1499+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
1500+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
15011501
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
15021502
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
15031503
store volatile <2 x double> %vec.2, ptr addrspace(1) undef
@@ -1617,10 +1617,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_v(<8 x double> %vec, double i
16171617
; GFX11-NEXT: s_endpgm
16181618
entry:
16191619
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
1620-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
1621-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
1622-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
1623-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
1620+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
1621+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
1622+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
1623+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
16241624
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
16251625
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
16261626
store volatile <2 x double> %vec.2, ptr addrspace(1) undef
@@ -1677,10 +1677,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_s(<8 x double> %vec, double %
16771677
; GFX11-NEXT: s_endpgm
16781678
entry:
16791679
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
1680-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
1681-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
1682-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
1683-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
1680+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
1681+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
1682+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
1683+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
16841684
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
16851685
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
16861686
store volatile <2 x double> %vec.2, ptr addrspace(1) undef
@@ -1794,10 +1794,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v(<8 x double> %vec, double %
17941794
; GFX11-NEXT: s_endpgm
17951795
entry:
17961796
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
1797-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
1798-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
1799-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
1800-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
1797+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
1798+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
1799+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
1800+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
18011801
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
18021802
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
18031803
store volatile <2 x double> %vec.2, ptr addrspace(1) undef
@@ -2401,10 +2401,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %v
24012401
entry:
24022402
%idx.add = add i32 %idx, 1
24032403
%insert = insertelement <8 x double> %vec, double %val, i32 %idx.add
2404-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
2405-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
2406-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
2407-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
2404+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
2405+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
2406+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
2407+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
24082408
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
24092409
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
24102410
store volatile <2 x double> %vec.2, ptr addrspace(1) undef
@@ -2525,10 +2525,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, do
25252525
entry:
25262526
%idx.add = add i32 %idx, 1
25272527
%insert = insertelement <8 x double> %vec, double %val, i32 %idx.add
2528-
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
2529-
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
2530-
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
2531-
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
2528+
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
2529+
%vec.1 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 2, i32 3>
2530+
%vec.2 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 4, i32 5>
2531+
%vec.3 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 6, i32 7>
25322532
store volatile <2 x double> %vec.0, ptr addrspace(1) undef
25332533
store volatile <2 x double> %vec.1, ptr addrspace(1) undef
25342534
store volatile <2 x double> %vec.2, ptr addrspace(1) undef

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1519,7 +1519,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
15191519
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
15201520
; CHECK-NEXT: S_ENDPGM 0
15211521
%load = load <2 x i64>, ptr addrspace(1) null
1522-
%val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 undef>, <3 x i32> <i32 0, i32 1, i32 2>
1522+
%val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 poison>, <3 x i32> <i32 0, i32 1, i32 2>
15231523

15241524
call void @external_void_func_v3i64(<3 x i64> %val)
15251525
ret void

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -322,7 +322,7 @@ define i32 @v_sdot2_shuffle10_a(<2 x i16> %a, <2 x i16> %b, i32 %c) {
322322
; GFX10-NEXT: v_alignbit_b32 v0, v0, v0, 16
323323
; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
324324
; GFX10-NEXT: s_setpc_b64 s[30:31]
325-
%shuf.a = shufflevector <2 x i16> %a, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
325+
%shuf.a = shufflevector <2 x i16> %a, <2 x i16> poison, <2 x i32> <i32 1, i32 0>
326326
%r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %shuf.a, <2 x i16> %b, i32 %c, i1 false)
327327
ret i32 %r
328328
}
@@ -349,7 +349,7 @@ define i32 @v_sdot2_shuffle10_b(<2 x i16> %a, <2 x i16> %b, i32 %c) {
349349
; GFX10-NEXT: v_alignbit_b32 v1, v1, v1, 16
350350
; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
351351
; GFX10-NEXT: s_setpc_b64 s[30:31]
352-
%shuf.b = shufflevector <2 x i16> %b, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
352+
%shuf.b = shufflevector <2 x i16> %b, <2 x i16> poison, <2 x i32> <i32 1, i32 0>
353353
%r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %shuf.b, i32 %c, i1 false)
354354
ret i32 %r
355355
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -306,7 +306,7 @@ define i32 @v_udot2_shuffle10_a(<2 x i16> %a, <2 x i16> %b, i32 %c) {
306306
; GFX10-NEXT: v_alignbit_b32 v0, v0, v0, 16
307307
; GFX10-NEXT: v_dot2_u32_u16 v0, v0, v1, v2
308308
; GFX10-NEXT: s_setpc_b64 s[30:31]
309-
%shuf.a = shufflevector <2 x i16> %a, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
309+
%shuf.a = shufflevector <2 x i16> %a, <2 x i16> poison, <2 x i32> <i32 1, i32 0>
310310
%r = call i32 @llvm.amdgcn.udot2(<2 x i16> %shuf.a, <2 x i16> %b, i32 %c, i1 false)
311311
ret i32 %r
312312
}
@@ -332,7 +332,7 @@ define i32 @v_udot2_shuffle10_b(<2 x i16> %a, <2 x i16> %b, i32 %c) {
332332
; GFX10-NEXT: v_alignbit_b32 v1, v1, v1, 16
333333
; GFX10-NEXT: v_dot2_u32_u16 v0, v0, v1, v2
334334
; GFX10-NEXT: s_setpc_b64 s[30:31]
335-
%shuf.b = shufflevector <2 x i16> %b, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
335+
%shuf.b = shufflevector <2 x i16> %b, <2 x i16> poison, <2 x i32> <i32 1, i32 0>
336336
%r = call i32 @llvm.amdgcn.udot2(<2 x i16> %a, <2 x i16> %shuf.b, i32 %c, i1 false)
337337
ret i32 %r
338338
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -121,15 +121,15 @@ define amdgpu_ps i32 @s_trunc_v2i32_to_v2i16(<2 x i32> inreg %src) {
121121
; ; FIXME: G_INSERT mishandled
122122
; define <2 x i32> @v_trunc_v3i32_to_v3i16(<3 x i32> %src) {
123123
; %trunc = trunc <3 x i32> %src to <3 x i16>
124-
; %ext = shufflevector <3 x i16> %trunc, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
124+
; %ext = shufflevector <3 x i16> %trunc, <3 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
125125
; %cast = bitcast <4 x i16> %ext to <2 x i32>
126126
; ret <2 x i32> %cast
127127
; }
128128

129129
; ; FIXME: G_INSERT mishandled
130130
; define amdgpu_ps <2 x i32> @s_trunc_v3i32_to_v3i16(<3 x i32> inreg %src) {
131131
; %trunc = trunc <3 x i32> %src to <3 x i16>
132-
; %ext = shufflevector <3 x i16> %trunc, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
132+
; %ext = shufflevector <3 x i16> %trunc, <3 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
133133
; %cast = bitcast <4 x i16> %ext to <2 x i32>
134134
; ret <2 x i32> %cast
135135
; }

‎llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -426,7 +426,7 @@ define amdgpu_ps void @test_wmma_f16_16x16x16_f16_negC_pack(<8 x half> %A, <8 x
426426
; GFX12-NEXT: s_endpgm
427427
bb:
428428
%C = load <16 x half>, ptr %Caddr
429-
%C_shuffle = shufflevector <16 x half> %C, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
429+
%C_shuffle = shufflevector <16 x half> %C, <16 x half> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
430430
%fneg.C_shuffle = fneg <8 x half> %C_shuffle
431431
%res = call <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v8f16(<8 x half> %A, <8 x half> %B, <8 x half> %fneg.C_shuffle , i1 0)
432432
store <8 x half> %res, ptr addrspace(1) %out

‎llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -381,7 +381,7 @@ define amdgpu_ps void @test_wmma_f16_16x16x16_f16_negC_pack(<4 x half> %A, <4 x
381381
; GFX12-NEXT: s_endpgm
382382
bb:
383383
%C = load <8 x half>, ptr %Caddr
384-
%C_shuffle = shufflevector <8 x half> %C, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
384+
%C_shuffle = shufflevector <8 x half> %C, <8 x half> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
385385
%fneg.C_shuffle = fneg <4 x half> %C_shuffle
386386
%res = call <4 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v8f16(<4 x half> %A, <4 x half> %B, <4 x half> %fneg.C_shuffle , i1 0)
387387
store <4 x half> %res, ptr addrspace(1) %out

‎llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ define amdgpu_ps void @adjust_writemask_crash_0_nochain() #0 {
99
main_body:
1010
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
1111
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
12-
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
12+
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
1313
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
1414
%tmp4 = extractelement <4 x float> %tmp3, i32 0
1515
store volatile float %tmp4, ptr addrspace(1) undef
@@ -25,7 +25,7 @@ define amdgpu_ps void @adjust_writemask_crash_1_nochain() #0 {
2525
main_body:
2626
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
2727
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
28-
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>
28+
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
2929
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
3030
%tmp4 = extractelement <4 x float> %tmp3, i32 1
3131
store volatile float %tmp4, ptr addrspace(1) undef
@@ -41,7 +41,7 @@ define amdgpu_ps void @adjust_writemask_crash_0_chain() #0 {
4141
main_body:
4242
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
4343
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
44-
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
44+
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
4545
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
4646
%tmp4 = extractelement <4 x float> %tmp3, i32 0
4747
store volatile float %tmp4, ptr addrspace(1) undef
@@ -57,7 +57,7 @@ define amdgpu_ps void @adjust_writemask_crash_1_chain() #0 {
5757
main_body:
5858
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
5959
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
60-
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>
60+
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
6161
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
6262
%tmp4 = extractelement <4 x float> %tmp3, i32 1
6363
store volatile float %tmp4, ptr addrspace(1) undef
@@ -68,7 +68,7 @@ define amdgpu_ps void @adjust_writemask_crash_0_v4() #0 {
6868
main_body:
6969
%tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
7070
%tmp1 = bitcast <4 x float> %tmp to <4 x i32>
71-
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
71+
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
7272
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
7373
%tmp4 = extractelement <4 x float> %tmp3, i32 0
7474
store volatile float %tmp4, ptr addrspace(1) undef

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