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[PowerPC] Add intrinsics and tests for basic Dense Math enablement instructions (llvm#129913)
Add intrinsics and tests for Dense Math basic enablement instructions dmsetdmrz, dmmr, dmxor.
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‎llvm/include/llvm/IR/IntrinsicsPowerPC.td

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@@ -1644,6 +1644,16 @@ let TargetPrefix = "ppc" in {
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def int_ppc_mma_xxsetaccz :
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DefaultAttrsIntrinsic<[llvm_v512i1_ty], [], [IntrNoMem]>;
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def int_ppc_mma_dmsetdmrz :
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DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [], [IntrNoMem]>;
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def int_ppc_mma_dmmr :
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DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty], [IntrNoMem]>;
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def int_ppc_mma_dmxor :
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DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty,
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llvm_v1024i1_ty], [IntrNoMem]>;
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// MMA Reduced-Precision: Outer Product Intrinsic Definitions.
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defm int_ppc_mma_xvi4ger8 :
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PowerPC_MMA_ACC_PP_Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty]>;

‎llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td

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@@ -105,12 +105,15 @@ let Predicates = [IsISAFuture] in {
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"dmxxinstfdmr256 $AT, $XBp, $P", []>;
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def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
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"dmmr $AT, $AB", []>;
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"dmmr $AT, $AB",
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[(set v1024i1:$AT, (int_ppc_mma_dmmr v1024i1:$AB))]>;
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def DMXOR : XForm_ATB3<31, 7, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB),
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"dmxor $AT, $AB", []>,
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"dmxor $AT, $AB",
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[(set v1024i1:$AT, (int_ppc_mma_dmxor v1024i1:$ATi, v1024i1:$AB))]>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
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"dmsetdmrz $AT", NoItinerary, []>;
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"dmsetdmrz $AT", NoItinerary,
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[(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>;
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}

‎llvm/test/CodeGen/PowerPC/dmr-enable.ll

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@@ -0,0 +1,134 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=future -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix \
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; RUN: -mcpu=future -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
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define void @tdmrz(ptr nocapture readonly %vp1, ptr nocapture %resp) {
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; CHECK-LABEL: tdmrz:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: dmsetdmrz dmr0
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; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
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; CHECK-NEXT: stxvp vsp34, 96(r4)
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; CHECK-NEXT: stxvp vsp36, 64(r4)
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; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
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; CHECK-NEXT: stxvp vsp34, 32(r4)
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; CHECK-NEXT: stxvp vsp36, 0(r4)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: tdmrz:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: dmsetdmrz dmr0
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; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
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; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
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; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
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; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
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; CHECK-BE-NEXT: stxvp vsp36, 32(r4)
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; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
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; CHECK-BE-NEXT: blr
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entry:
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%z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
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store <1024 x i1> %z, ptr %resp, align 32
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ret void
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}
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define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
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; CHECK-LABEL: tdmmr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvp vsp34, 0(r3)
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; CHECK-NEXT: lxvp vsp36, 32(r3)
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; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
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; CHECK-NEXT: lxvp vsp34, 64(r3)
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; CHECK-NEXT: lxvp vsp36, 96(r3)
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; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
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; CHECK-NEXT: dmmr dmr0, dmr0
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; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
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; CHECK-NEXT: stxvp vsp34, 96(r4)
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; CHECK-NEXT: stxvp vsp36, 64(r4)
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; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
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; CHECK-NEXT: stxvp vsp34, 32(r4)
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; CHECK-NEXT: stxvp vsp36, 0(r4)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: tdmmr:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
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; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
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; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
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; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
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; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
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; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
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; CHECK-BE-NEXT: dmmr dmr0, dmr0
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; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
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; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
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; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
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; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
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; CHECK-BE-NEXT: stxvp vsp36, 32(r4)
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; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
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; CHECK-BE-NEXT: blr
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entry:
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%l = load <1024 x i1>, ptr %vp1, align 32
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%c = call <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1> %l)
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store <1024 x i1> %c, ptr %resp, align 32
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ret void
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}
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define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp) {
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; CHECK-LABEL: tdmxor:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvp vsp34, 0(r3)
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; CHECK-NEXT: lxvp vsp36, 32(r3)
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; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
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; CHECK-NEXT: lxvp vsp34, 64(r3)
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; CHECK-NEXT: lxvp vsp36, 96(r3)
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; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
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; CHECK-NEXT: lxvp vsp34, 0(r4)
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; CHECK-NEXT: lxvp vsp36, 32(r4)
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; CHECK-NEXT: dmxxinstfdmr512 wacc_hi1, vsp36, vsp34, 1
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; CHECK-NEXT: lxvp vsp34, 64(r4)
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; CHECK-NEXT: lxvp vsp36, 96(r4)
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; CHECK-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
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; CHECK-NEXT: dmxor dmr0, dmr1
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; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
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; CHECK-NEXT: stxvp vsp34, 96(r5)
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; CHECK-NEXT: stxvp vsp36, 64(r5)
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; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
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; CHECK-NEXT: stxvp vsp34, 32(r5)
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; CHECK-NEXT: stxvp vsp36, 0(r5)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: tdmxor:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
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; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
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; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
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; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
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; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
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; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
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; CHECK-BE-NEXT: lxvp vsp34, 96(r4)
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; CHECK-BE-NEXT: lxvp vsp36, 64(r4)
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; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi1, vsp36, vsp34, 1
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; CHECK-BE-NEXT: lxvp vsp34, 32(r4)
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; CHECK-BE-NEXT: lxvp vsp36, 0(r4)
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; CHECK-BE-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
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; CHECK-BE-NEXT: dmxor dmr0, dmr1
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; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
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; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
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; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
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; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
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; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
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; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
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; CHECK-BE-NEXT: blr
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entry:
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%l = load <1024 x i1>, ptr %vp1, align 32
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%r = load <1024 x i1>, ptr %vp2, align 32
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%x = call <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1> %l, <1024 x i1> %r)
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store <1024 x i1> %x, ptr %resp, align 32
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ret void
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}
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declare <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
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declare <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1>)
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declare <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1>, <1024 x i1>)

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