Skip to content

Commit 4a7d831

Browse files
mhr3mhr3
committed
use symbolic names
1 parent 1209840 commit 4a7d831

File tree

4 files changed

+44
-34
lines changed

4 files changed

+44
-34
lines changed

‎x86/x86asm/decode.go

+23-25
Original file line numberDiff line numberDiff line change
@@ -461,10 +461,10 @@ ReadPrefixes:
461461

462462
vexEscapeSeq := make([]byte, 0, 2)
463463
switch vex {
464-
case 0xC5:
464+
case PrefixVEX2:
465465
vexEscapeSeq = append(vexEscapeSeq, 0x0f)
466-
case 0xC4:
467-
vexM := inst.Prefix[vexIndex+1] & 0x1f
466+
case PrefixVEX3:
467+
vexM := inst.Prefix[vexIndex+1] & PrefixVEXM
468468
switch vexM {
469469
case 0x01:
470470
vexEscapeSeq = append(vexEscapeSeq, 0x0f)
@@ -520,7 +520,7 @@ Decode:
520520
if rex&PrefixREXR != 0 {
521521
rexUsed |= PrefixREXR
522522
regop |= 8
523-
} else if vex != 0 && inst.Prefix[vexIndex+1]&0x80 == 0 {
523+
} else if vex != 0 && inst.Prefix[vexIndex+1]&PrefixVEXnotR == 0 {
524524
regop |= 8
525525
}
526526
if addrMode == 16 {
@@ -569,11 +569,11 @@ Decode:
569569
scale = sib >> 6
570570
index = (sib >> 3) & 07
571571
base = sib & 07
572-
if rex&PrefixREXB != 0 || vex == 0xC4 && inst.Prefix[vexIndex+1]&0x20 == 0 {
572+
if rex&PrefixREXB != 0 || vex == PrefixVEX3 && inst.Prefix[vexIndex+1]&PrefixVEXnotB == 0 {
573573
rexUsed |= PrefixREXB
574574
base |= 8
575575
}
576-
if rex&PrefixREXX != 0 || vex == 0xC4 && inst.Prefix[vexIndex+1]&0x40 == 0 {
576+
if rex&PrefixREXX != 0 || vex == PrefixVEX3 && inst.Prefix[vexIndex+1]&PrefixVEXnotX == 0 {
577577
rexUsed |= PrefixREXX
578578
index |= 8
579579
}
@@ -593,7 +593,10 @@ Decode:
593593
if rex&PrefixREXB != 0 {
594594
rexUsed |= PrefixREXB
595595
rm |= 8
596+
} else if vex == PrefixVEX3 && inst.Prefix[vexIndex+1]&PrefixVEXnotB == 0 {
597+
rm |= 8
596598
}
599+
597600
if mod == 0 && rm&7 == 5 || rm&7 == 4 {
598601
// base omitted
599602
} else if mod != 3 {
@@ -861,13 +864,13 @@ Decode:
861864
}
862865

863866
var vexW, vexL, vexP Prefix
864-
if vex == 0xC4 {
865-
vexW = inst.Prefix[vexIndex+2] & 0x80
866-
vexL = inst.Prefix[vexIndex+2] & 0x04
867-
vexP = inst.Prefix[vexIndex+2] & 0x03
867+
if vex == PrefixVEX3 {
868+
vexW = inst.Prefix[vexIndex+2] & PrefixVEXW
869+
vexL = inst.Prefix[vexIndex+2] & PrefixVEXL
870+
vexP = inst.Prefix[vexIndex+2] & PrefixVEXP
868871
} else {
869-
vexL = inst.Prefix[vexIndex+1] & 0x04
870-
vexP = inst.Prefix[vexIndex+1] & 0x03
872+
vexL = inst.Prefix[vexIndex+1] & PrefixVEXL
873+
vexP = inst.Prefix[vexIndex+1] & PrefixVEXP
871874
}
872875

873876
switch vexFlag {
@@ -902,7 +905,7 @@ Decode:
902905

903906
if ok {
904907
// TODO: bit of a hack, some instructions ignore the L bit
905-
if vexL&4 == 0 {
908+
if vexL == 0 {
906909
dataMode = 128
907910
} else {
908911
dataMode = 256
@@ -1197,18 +1200,17 @@ Decode:
11971200
base := baseReg[x]
11981201

11991202
var vexV Prefix
1200-
if vex == 0xC5 {
1201-
vexV = inst.Prefix[vexIndex+1]
1202-
} else if vex == 0xC4 {
1203-
vexV = inst.Prefix[vexIndex+2]
1204-
} else {
1203+
switch vex {
1204+
case PrefixVEX2:
1205+
vexV = (inst.Prefix[vexIndex+1] & PrefixVEXnotV) >> 3
1206+
case PrefixVEX3:
1207+
vexV = (inst.Prefix[vexIndex+2] & PrefixVEXnotV) >> 3
1208+
default:
12051209
println("bad vex", vex)
12061210
return Inst{Len: pos}, errInternal
12071211
}
12081212

1209-
vexV = (vexV & 0x78) >> 3
1210-
vexV ^= 0xF
1211-
index := Reg(vexV)
1213+
index := Reg(vexV ^ 0xf)
12121214

12131215
inst.Args[narg] = base + index
12141216
narg++
@@ -1299,10 +1301,6 @@ Decode:
12991301
index -= 4
13001302
base = SPB
13011303
}
1302-
case xArgXmm2M8, xArgXmm2M16, xArgXmm2M32, xArgXmm2M64, xArgXmm2M128, xArgYmm2M256:
1303-
if vex == 0xC4 && inst.Prefix[vexIndex+1]&0x20 == 0 {
1304-
index += 8
1305-
}
13061304
}
13071305
inst.Args[narg] = base + index
13081306
}

‎x86/x86asm/inst.go

+17-8
Original file line numberDiff line numberDiff line change
@@ -72,13 +72,22 @@ const (
7272

7373
// The REX prefixes must be in the range [PrefixREX, PrefixREX+0x10).
7474
// the other bits are set or not according to the intended use.
75-
PrefixREX Prefix = 0x40 // REX 64-bit extension prefix
76-
PrefixREXW Prefix = 0x08 // extension bit W (64-bit instruction width)
77-
PrefixREXR Prefix = 0x04 // extension bit R (r field in modrm)
78-
PrefixREXX Prefix = 0x02 // extension bit X (index field in sib)
79-
PrefixREXB Prefix = 0x01 // extension bit B (r/m field in modrm or base field in sib)
80-
PrefixVEX2Bytes Prefix = 0xC5 // Short form of vex prefix
81-
PrefixVEX3Bytes Prefix = 0xC4 // Long form of vex prefix
75+
PrefixREX Prefix = 0x40 // REX 64-bit extension prefix
76+
PrefixREXW Prefix = 0x08 // extension bit W (64-bit instruction width)
77+
PrefixREXR Prefix = 0x04 // extension bit R (r field in modrm)
78+
PrefixREXX Prefix = 0x02 // extension bit X (index field in sib)
79+
PrefixREXB Prefix = 0x01 // extension bit B (r/m field in modrm or base field in sib)
80+
81+
PrefixVEX2 Prefix = 0xC5 // Short form of VEX prefix
82+
PrefixVEX3 Prefix = 0xC4 // Long form of VEX prefix
83+
PrefixVEXnotR Prefix = 0x80 // VEX not R
84+
PrefixVEXnotX Prefix = 0x40 // VEX not X
85+
PrefixVEXnotB Prefix = 0x20 // VEX not B
86+
PrefixVEXM Prefix = 0x1f // VEX M
87+
PrefixVEXW Prefix = 0x80 // VEX W
88+
PrefixVEXnotV Prefix = 0x78 // VEX not vvvv
89+
PrefixVEXL Prefix = 0x04 // VEX L
90+
PrefixVEXP Prefix = 0x03 // VEX PP
8291
)
8392

8493
// IsREX reports whether p is a REX prefix byte.
@@ -87,7 +96,7 @@ func (p Prefix) IsREX() bool {
8796
}
8897

8998
func (p Prefix) IsVEX() bool {
90-
return p&0xFF == PrefixVEX2Bytes || p&0xFF == PrefixVEX3Bytes
99+
return p&0xFF == PrefixVEX2 || p&0xFF == PrefixVEX3
91100
}
92101

93102
func (p Prefix) String() string {

‎x86/x86asm/intel.go

+1-1
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ func IntelSyntax(inst Inst, pc uint64, symname SymLookup) string {
9393
inst.Prefix[i] |= PrefixImplicit
9494
}
9595
if p.IsVEX() {
96-
if p == PrefixVEX3Bytes {
96+
if p == PrefixVEX3 {
9797
inst.Prefix[i+2] |= PrefixImplicit
9898
}
9999
inst.Prefix[i] |= PrefixImplicit

‎x86/x86asm/testdata/decode.txt

+3
Original file line numberDiff line numberDiff line change
@@ -6770,6 +6770,9 @@ c4e27d78c8|556677885f5f5f5f5f5f5f 64 gnu vpbroadcastb %xmm0,%ymm1
67706770
c441305ec2|556677885f5f5f5f5f5f5f 64 intel vdivps xmm8, xmm9, xmm10
67716771
c441305ec2|556677885f5f5f5f5f5f5f 64 plan9 VDIVPS X10, X9, X8
67726772
c441305ec2|556677885f5f5f5f5f5f5f 64 gnu vdivps %xmm10,%xmm9,%xmm8
6773+
c4c17a1009|556677885f5f5f5f5f5f5f 64 intel vmovss xmm1, dword ptr [r9]
6774+
c4c17a1009|556677885f5f5f5f5f5f5f 64 plan9 VMOVSS 0(R9), X1
6775+
c4c17a1009|556677885f5f5f5f5f5f5f 64 gnu vmovss (%r9),%xmm1
67736776
c5f5efe2|44556677885f5f5f5f5f5f5f 64 intel vpxor ymm4, ymm1, ymm2
67746777
c5f5efe2|44556677885f5f5f5f5f5f5f 64 plan9 VPXOR Y2, Y1, Y4
67756778
c5f5efe2|44556677885f5f5f5f5f5f5f 64 gnu vpxor %ymm2,%ymm1,%ymm4

0 commit comments

Comments
 (0)