@@ -1839,35 +1839,59 @@ def Zn4WriteFZeroIdiom : SchedWriteVariant<[
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]>;
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// NOTE: XORPSrr, XORPDrr are not zero-cycle!
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def : InstRW<[Zn4WriteFZeroIdiom], (instrs VXORPSrr, VXORPDrr,
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- VANDNPSrr, VANDNPDrr)>;
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+ VXORPSZ128rr,
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+ VXORPDZ128rr,
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+ VANDNPSrr, VANDNPDrr,
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+ VANDNPSZ128rr,
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+ VANDNPDZ128rr)>;
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def Zn4WriteFZeroIdiomY : SchedWriteVariant<[
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SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [Zn4WriteZeroLatency]>,
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SchedVar<NoSchedPred, [WriteFLogicY]>
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]>;
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def : InstRW<[Zn4WriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
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- VANDNPSYrr, VANDNPDYrr)>;
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+ VXORPSZ256rr,
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+ VXORPDZ256rr,
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+ VANDNPSYrr, VANDNPDYrr,
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+ VANDNPSZ256rr,
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+ VANDNPDZ256rr)>;
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+
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+ def Zn4WriteFZeroIdiomZ : SchedWriteVariant<[
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+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [Zn4WriteZeroLatency]>,
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+ SchedVar<NoSchedPred, [WriteFLogicZ]>
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+ ]>;
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+ def : InstRW<[Zn4WriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr,
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+ VANDNPSZrr, VANDNPDZrr)>;
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def Zn4WriteVZeroIdiomLogicX : SchedWriteVariant<[
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SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [Zn4WriteZeroLatency]>,
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SchedVar<NoSchedPred, [WriteVecLogicX]>
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]>;
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// NOTE: PXORrr,PANDNrr are not zero-cycle!
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- def : InstRW<[Zn4WriteVZeroIdiomLogicX], (instrs VPXORrr, VPANDNrr)>;
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+ def : InstRW<[Zn4WriteVZeroIdiomLogicX], (instrs VPXORrr,
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+ VPXORDZ128rr,
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+ VPXORQZ128rr,
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+ VPANDNrr,
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+ VPANDNDZ128rr,
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+ VPANDNQZ128rr)>;
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- // TODO: This should be extended to incorporate all of the AVX512 zeroing
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- // idioms that can be executed by the renamer.
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- def Zn4WriteVZeroIdiomLogicZ : SchedWriteVariant<[
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+ def Zn4WriteVZeroIdiomLogicY : SchedWriteVariant<[
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SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [Zn4WriteZeroLatency]>,
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- SchedVar<NoSchedPred, [WriteVecLogicZ ]>
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+ SchedVar<NoSchedPred, [WriteVecLogicY ]>
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]>;
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- def : InstRW<[Zn4WriteVZeroIdiomLogicZ], (instrs VPXORDZrr)>;
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+ def : InstRW<[Zn4WriteVZeroIdiomLogicY], (instrs VPXORYrr,
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+ VPXORDZ256rr,
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+ VPXORQZ256rr,
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+ VPANDNYrr,
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+ VPANDNDZ256rr,
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+ VPANDNQZ256rr)>;
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- def Zn4WriteVZeroIdiomLogicY : SchedWriteVariant<[
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+ def Zn4WriteVZeroIdiomLogicZ : SchedWriteVariant<[
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SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [Zn4WriteZeroLatency]>,
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- SchedVar<NoSchedPred, [WriteVecLogicY ]>
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+ SchedVar<NoSchedPred, [WriteVecLogicZ ]>
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]>;
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- def : InstRW<[Zn4WriteVZeroIdiomLogicY], (instrs VPXORYrr, VPANDNYrr)>;
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+ def : InstRW<[Zn4WriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr,
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+ VPANDNDZrr, VPANDNQZrr)>;
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def Zn4WriteVZeroIdiomALUX : SchedWriteVariant<[
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SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [Zn4WriteZeroLatency]>,
@@ -1877,15 +1901,29 @@ def Zn4WriteVZeroIdiomALUX : SchedWriteVariant<[
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// PCMPGTBrr, PCMPGTWrr, PCMPGTDrr, PCMPGTQrr are not zero-cycle!
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def : InstRW<[Zn4WriteVZeroIdiomALUX],
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(instrs VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
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- VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr)>;
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+ VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr,
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+ VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
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+ VPCMPGTBZ128rr, VPCMPGTWZ128rr,
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+ VPCMPGTDZ128rr, VPCMPGTQZ128rr)>;
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def Zn4WriteVZeroIdiomALUY : SchedWriteVariant<[
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SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [Zn4WriteZeroLatency]>,
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SchedVar<NoSchedPred, [WriteVecALUY]>
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]>;
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def : InstRW<[Zn4WriteVZeroIdiomALUY],
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(instrs VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
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- VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr)>;
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+ VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr,
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+ VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr,
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+ VPCMPGTBZ256rr, VPCMPGTWZ256rr,
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+ VPCMPGTDZ256rr, VPCMPGTQZ256rr)>;
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+
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+ def Zn4WriteVZeroIdiomALUZ : SchedWriteVariant<[
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+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [Zn4WriteZeroLatency]>,
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+ SchedVar<NoSchedPred, [WriteVecALUZ]>
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+ ]>;
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+ def : InstRW<[Zn4WriteVZeroIdiomALUY],
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+ (instrs VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr,
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+ VPCMPGTBZrr, VPCMPGTWZrr, VPCMPGTDZrr, VPCMPGTQZrr)>;
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def : IsZeroIdiomFunction<[
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// GPR Zero-idioms.
@@ -1940,9 +1978,24 @@ def : IsZeroIdiomFunction<[
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], ZeroIdiomPredicate>,
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// AVX ZMM Zero-idioms.
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- // TODO: This should be expanded to incorporate all AVX512 zeroing idioms.
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DepBreakingClass<[
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- VPXORDZrr
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+ // fp variants.
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+ VXORPSZrr, VXORPDZrr,
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+ VXORPSZ128rr, VXORPDZ128rr, VXORPSZ256rr, VXORPDZ256rr,
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+ VANDNPSZrr, VANDNPDZrr,
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+ VANDNPSZ128rr, VANDNPDZ128rr, VANDNPSZ256rr, VANDNPDZ256rr,
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+
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+ // int variants.
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+ VPCMPGTBZrr, VPCMPGTWZrr, VPCMPGTDZrr, VPCMPGTQZrr,
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+ VPCMPGTBZ128rr, VPCMPGTWZ128rr, VPCMPGTDZ128rr, VPCMPGTQZ128rr,
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+ VPCMPGTBZ256rr, VPCMPGTWZ256rr, VPCMPGTDZ256rr, VPCMPGTQZ256rr,
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+ VPANDNDZrr, VPANDNQZrr,
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+ VPANDNDZ128rr, VPANDNQZ128rr, VPANDNDZ256rr, VPANDNQZ256rr,
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+ VPXORDZrr, VPXORQZrr,
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+ VPXORDZ128rr, VPXORQZ128rr, VPXORDZ256rr, VPXORQZ256rr,
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+ VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr,
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+ VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr,
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+ VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr,
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], ZeroIdiomPredicate>,
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]>;
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