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refactor: correct naming of enum class constants 3/n
Signed-off-by: Mateusz Jablonski <[email protected]>
1 parent 1ae79d4 commit 4320f48

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8 files changed

+121
-139
lines changed

8 files changed

+121
-139
lines changed

‎level_zero/core/test/black_box_tests/zello_bindless_kernel.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -78,25 +78,25 @@ static std::string kernelName2 = "kernel_fill";
7878
static std::string kernelName3 = "image_copy";
7979

8080
enum class ExecutionMode : uint32_t {
81-
CommandQueue,
82-
ImmSyncCmdList
81+
commandQueue,
82+
immSyncCmdList
8383
};
8484

8585
enum class AddressingMode : uint32_t {
86-
Default,
87-
Bindless,
88-
BindlessImages
86+
defaultMode,
87+
bindless,
88+
bindlessImages
8989
};
9090

9191
void createModule(const char *sourceCode, AddressingMode addressing, const ze_context_handle_t context, const ze_device_handle_t device, const std::string &deviceName, const std::string &revisionId, ze_module_handle_t &module) {
9292
std::string buildLog;
9393
std::string bindlessOptions = "-cl-intel-use-bindless-mode -cl-intel-use-bindless-advanced-mode";
9494
std::string bindlessImagesOptions = "-cl-intel-use-bindless-images -cl-intel-use-bindless-advanced-mode";
9595
std::string internalOptions = "";
96-
if (addressing == AddressingMode::Bindless) {
96+
if (addressing == AddressingMode::bindless) {
9797
internalOptions = bindlessOptions;
9898
}
99-
if (addressing == AddressingMode::BindlessImages) {
99+
if (addressing == AddressingMode::bindlessImages) {
100100
internalOptions = bindlessImagesOptions;
101101
}
102102
auto bin = LevelZeroBlackBoxTests::compileToNative(sourceCode, deviceName, revisionId, "", internalOptions, buildLog);
@@ -125,7 +125,7 @@ void run(const ze_kernel_handle_t &copyKernel, const ze_kernel_handle_t &fillKer
125125
ze_context_handle_t &context, ze_device_handle_t &device, uint32_t id, ExecutionMode mode, bool &outputValidationSuccessful) {
126126

127127
LevelZeroBlackBoxTests::CommandHandler commandHandler;
128-
bool isImmediateCmdList = (mode == ExecutionMode::ImmSyncCmdList);
128+
bool isImmediateCmdList = (mode == ExecutionMode::immSyncCmdList);
129129

130130
SUCCESS_OR_TERMINATE(commandHandler.create(context, device, isImmediateCmdList));
131131

@@ -200,10 +200,10 @@ bool testBindlessBufferCopy(ze_context_handle_t context, ze_device_handle_t devi
200200

201201
ze_module_handle_t module = nullptr;
202202
ze_module_handle_t module2 = nullptr;
203-
createModule(source, AddressingMode::Bindless, context, device, deviceId, revisionId, module);
204-
createModule(source2, AddressingMode::Default, context, device, deviceId, revisionId, module2);
203+
createModule(source, AddressingMode::bindless, context, device, deviceId, revisionId, module);
204+
createModule(source2, AddressingMode::defaultMode, context, device, deviceId, revisionId, module2);
205205

206-
ExecutionMode executionModes[] = {ExecutionMode::CommandQueue, ExecutionMode::ImmSyncCmdList};
206+
ExecutionMode executionModes[] = {ExecutionMode::commandQueue, ExecutionMode::immSyncCmdList};
207207
ze_kernel_handle_t copyKernel = nullptr;
208208
ze_kernel_handle_t fillKernel = nullptr;
209209
createKernel(module, copyKernel, kernelName.c_str());
@@ -387,7 +387,7 @@ int main(int argc, char *argv[]) {
387387
auto imageCount = LevelZeroBlackBoxTests::getParamValue(argc, argv, "", "--image-count", defaultImageCount);
388388
auto bindlessImages = LevelZeroBlackBoxTests::isParamEnabled(argc, argv, "", "--bindless-images");
389389

390-
AddressingMode mode = bindlessImages ? AddressingMode::BindlessImages : AddressingMode::Bindless;
390+
AddressingMode mode = bindlessImages ? AddressingMode::bindlessImages : AddressingMode::bindless;
391391
std::cout << "--image-count: " << imageCount << std::endl;
392392

393393
if (bindlessImages) {

‎level_zero/core/test/black_box_tests/zello_printf.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -40,8 +40,8 @@ static constexpr std::array<const char *, 2> kernelNames = {"printf_kernel",
4040
"printf_kernel1"};
4141

4242
enum class PrintfExecutionMode : uint32_t {
43-
CommandQueue,
44-
ImmSyncCmdList
43+
commandQueue,
44+
immSyncCmdList
4545
};
4646

4747
void createModule(const ze_context_handle_t context, const ze_device_handle_t device, ze_module_handle_t &module) {
@@ -72,7 +72,7 @@ void runPrintfKernel(const ze_module_handle_t &module, const ze_kernel_handle_t
7272
ze_context_handle_t &context, ze_device_handle_t &device, uint32_t id, PrintfExecutionMode mode) {
7373

7474
LevelZeroBlackBoxTests::CommandHandler commandHandler;
75-
bool isImmediateCmdList = (mode == PrintfExecutionMode::ImmSyncCmdList);
75+
bool isImmediateCmdList = (mode == PrintfExecutionMode::immSyncCmdList);
7676

7777
SUCCESS_OR_TERMINATE(commandHandler.create(context, device, isImmediateCmdList));
7878

@@ -129,7 +129,7 @@ int main(int argc, char *argv[]) {
129129
"id == 0\nid == 0\nid == 0\nid == 0\nid == 0\n"
130130
"id == 0\nid == 0\nid == 0\nid == 0\nid == 0\n"};
131131

132-
PrintfExecutionMode executionModes[] = {PrintfExecutionMode::CommandQueue, PrintfExecutionMode::ImmSyncCmdList};
132+
PrintfExecutionMode executionModes[] = {PrintfExecutionMode::commandQueue, PrintfExecutionMode::immSyncCmdList};
133133

134134
for (auto mode : executionModes) {
135135
for (uint32_t i = 0; i < 2; i++) {

‎opencl/test/unit_test/aub_tests/command_stream/mi_math_aub_tests_dg2_and_later.cpp

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -18,15 +18,15 @@
1818

1919
namespace NEO {
2020
enum class NewAluOpcodes : uint32_t {
21-
OPCODE_LOAD = 0x080,
22-
OPCODE_LOAD0 = 0x081,
23-
OPCODE_LOAD1 = 0x481,
24-
OPCODE_LOADIND = 0x082,
25-
OPCODE_STOREIND = 0x181,
26-
OPCODE_SHL = 0x105,
27-
OPCODE_SHR = 0x106,
28-
OPCODE_SAR = 0x107,
29-
OPCODE_FENCE = 0x001
21+
opcodeLoad = 0x080,
22+
opcodeLoad0 = 0x081,
23+
opcodeLoad1 = 0x481,
24+
opcodeLoadind = 0x082,
25+
opcodeStoreind = 0x181,
26+
opcodeShl = 0x105,
27+
opcodeShr = 0x106,
28+
opcodeSar = 0x107,
29+
opcodeFence = 0x001
3030
};
3131

3232
struct MiMath : public AUBFixture, public ::testing::Test {
@@ -100,7 +100,7 @@ struct MiMath : public AUBFixture, public ::testing::Test {
100100
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCB);
101101
pAluParam->DW0.BitField.Operand2 = shiftReg;
102102
pAluParam++;
103-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_SHL); // shift high part
103+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeShl); // shift high part
104104
pAluParam->DW0.BitField.Operand1 = 0;
105105
pAluParam->DW0.BitField.Operand2 = 0;
106106
pAluParam++;
@@ -158,15 +158,15 @@ HWTEST2_F(MiMath, givenLoadIndirectFromMemoryWhenUseMiMathToSimpleOperationThenS
158158
reinterpret_cast<MI_MATH *>(pCmd)->DW0.BitField.DwordLength = numberOfOperationToLoadAddressToMiMathAccu + 13 - 1;
159159
loadAddressToMiMathAccu<FamilyType>(static_cast<uint32_t>(AluRegisters::R_0), static_cast<uint32_t>(AluRegisters::R_1), static_cast<uint32_t>(AluRegisters::R_2)); // GPU address of buffer load to ACCU register
160160
MI_MATH_ALU_INST_INLINE *pAluParam = reinterpret_cast<MI_MATH_ALU_INST_INLINE *>(taskStream->getSpace(13 * sizeof(MI_MATH_ALU_INST_INLINE)));
161-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_FENCE); // to be sure that all writes and reads are completed
161+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeFence); // to be sure that all writes and reads are completed
162162
pAluParam->DW0.BitField.Operand1 = 0;
163163
pAluParam->DW0.BitField.Operand2 = 0;
164164
pAluParam++;
165-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_LOADIND); // load dword from memory address located in ACCU
165+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeLoadind); // load dword from memory address located in ACCU
166166
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_0);
167167
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_ACCU);
168168
pAluParam++;
169-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_FENCE); // to be sure that all writes and reads are completed
169+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeFence); // to be sure that all writes and reads are completed
170170
pAluParam->DW0.BitField.Operand1 = 0;
171171
pAluParam->DW0.BitField.Operand2 = 0;
172172
pAluParam++;
@@ -194,19 +194,19 @@ HWTEST2_F(MiMath, givenLoadIndirectFromMemoryWhenUseMiMathToSimpleOperationThenS
194194
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCA);
195195
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_2);
196196
pAluParam++;
197-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_LOAD0);
197+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeLoad0);
198198
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCB);
199199
pAluParam->DW0.BitField.Operand2 = 0;
200200
pAluParam++;
201201
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(AluRegisters::OPCODE_ADD); // move address to ACCU
202202
pAluParam->DW0.BitField.Operand1 = 0;
203203
pAluParam->DW0.BitField.Operand2 = 0;
204204
pAluParam++;
205-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_FENCE); // to be sure that all writes and reads are completed
205+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeFence); // to be sure that all writes and reads are completed
206206
pAluParam->DW0.BitField.Operand1 = 0;
207207
pAluParam->DW0.BitField.Operand2 = 0;
208208
pAluParam++;
209-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_STOREIND); // store to memory from ACCU, value from register R1
209+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeStoreind); // store to memory from ACCU, value from register R1
210210
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_ACCU);
211211
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_1);
212212

@@ -248,30 +248,30 @@ HWTEST2_F(MiMath, givenLoadIndirectFromMemoryWhenUseMiMathThenStoreIndirectToAno
248248
loadAddressToMiMathAccu<FamilyType>(static_cast<uint32_t>(AluRegisters::R_0), static_cast<uint32_t>(AluRegisters::R_1), static_cast<uint32_t>(AluRegisters::R_2)); // GPU address of buffer load to ACCU register
249249

250250
MI_MATH_ALU_INST_INLINE *pAluParam = reinterpret_cast<MI_MATH_ALU_INST_INLINE *>(taskStream->getSpace(3 * sizeof(MI_MATH_ALU_INST_INLINE)));
251-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_FENCE); // to be sure that all writes and reads are completed
251+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeFence); // to be sure that all writes and reads are completed
252252
pAluParam->DW0.BitField.Operand1 = 0;
253253
pAluParam->DW0.BitField.Operand2 = 0;
254254
pAluParam++;
255-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_LOADIND); // load dword from memory address located in ACCU to R0
255+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeLoadind); // load dword from memory address located in ACCU to R0
256256
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_0);
257257
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_ACCU);
258258
pAluParam++;
259-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_FENCE); // to be sure that all writes and reads are completed
259+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeFence); // to be sure that all writes and reads are completed
260260
pAluParam->DW0.BitField.Operand1 = 0;
261261
pAluParam->DW0.BitField.Operand2 = 0;
262262

263263
loadAddressToMiMathAccu<FamilyType>(static_cast<uint32_t>(AluRegisters::R_3), static_cast<uint32_t>(AluRegisters::R_4), static_cast<uint32_t>(AluRegisters::R_2)); // GPU address of bufferB load to ACCU register
264264

265265
pAluParam = reinterpret_cast<MI_MATH_ALU_INST_INLINE *>(taskStream->getSpace(3 * sizeof(MI_MATH_ALU_INST_INLINE)));
266-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_FENCE); // to be sure that all writes and reads are completed
266+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeFence); // to be sure that all writes and reads are completed
267267
pAluParam->DW0.BitField.Operand1 = 0;
268268
pAluParam->DW0.BitField.Operand2 = 0;
269269
pAluParam++;
270-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_STOREIND); // store to memory from ACCU, value from register R0
270+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeStoreind); // store to memory from ACCU, value from register R0
271271
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_ACCU);
272272
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_0);
273273
pAluParam++;
274-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_FENCE); // to be sure that all writes and reads are completed
274+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeFence); // to be sure that all writes and reads are completed
275275
pAluParam->DW0.BitField.Operand1 = 0;
276276
pAluParam->DW0.BitField.Operand2 = 0;
277277

@@ -317,7 +317,7 @@ HWTEST2_F(MiMath, givenValueToMakeLeftLogicalShiftWhenUseMiMathThenShiftIsDonePr
317317
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCB);
318318
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_1);
319319
pAluParam++;
320-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_SHL); // load value to shift to SRCB
320+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeShl); // load value to shift to SRCB
321321
pAluParam->DW0.BitField.Operand1 = 0;
322322
pAluParam->DW0.BitField.Operand2 = 0;
323323
pAluParam++;
@@ -329,7 +329,7 @@ HWTEST2_F(MiMath, givenValueToMakeLeftLogicalShiftWhenUseMiMathThenShiftIsDonePr
329329
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCB);
330330
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_2);
331331
pAluParam++;
332-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_SHL); // load value to shift to SRCB
332+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeShl); // load value to shift to SRCB
333333
pAluParam->DW0.BitField.Operand1 = 0;
334334
pAluParam->DW0.BitField.Operand2 = 0;
335335
pAluParam++;
@@ -388,7 +388,7 @@ HWTEST2_F(MiMath, givenValueToMakeRightLogicalShiftWhenUseMiMathThenShiftIsDoneP
388388
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCB);
389389
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_1);
390390
pAluParam++;
391-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_SHR); // load value to shift to SRCB
391+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeShr); // load value to shift to SRCB
392392
pAluParam->DW0.BitField.Operand1 = 0;
393393
pAluParam->DW0.BitField.Operand2 = 0;
394394
pAluParam++;
@@ -400,7 +400,7 @@ HWTEST2_F(MiMath, givenValueToMakeRightLogicalShiftWhenUseMiMathThenShiftIsDoneP
400400
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCB);
401401
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_2);
402402
pAluParam++;
403-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_SHR); // load value to shift to SRCB
403+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeShr); // load value to shift to SRCB
404404
pAluParam->DW0.BitField.Operand1 = 0;
405405
pAluParam->DW0.BitField.Operand2 = 0;
406406
pAluParam++;
@@ -452,11 +452,11 @@ HWTEST2_F(MiMath, givenValueToMakeRightAritmeticShiftWhenUseMiMathThenShiftIsDon
452452
reinterpret_cast<MI_MATH *>(pCmd)->DW0.BitField.DwordLength = numberOfOperationToLoadAddressToMiMathAccu + 9 - 1;
453453
loadAddressToMiMathAccu<FamilyType>(static_cast<uint32_t>(AluRegisters::R_0), static_cast<uint32_t>(AluRegisters::R_1), static_cast<uint32_t>(AluRegisters::R_2)); // GPU address of buffer load to ACCU register
454454
MI_MATH_ALU_INST_INLINE *pAluParam = reinterpret_cast<MI_MATH_ALU_INST_INLINE *>(taskStream->getSpace(9 * sizeof(MI_MATH_ALU_INST_INLINE)));
455-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_LOADIND); // load value from R0 to SRCA
455+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeLoadind); // load value from R0 to SRCA
456456
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_3);
457457
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_ACCU);
458458
pAluParam++;
459-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_FENCE); // to be sure that all writes and reads are completed
459+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeFence); // to be sure that all writes and reads are completed
460460
pAluParam->DW0.BitField.Operand1 = 0;
461461
pAluParam->DW0.BitField.Operand2 = 0;
462462
pAluParam++;
@@ -468,7 +468,7 @@ HWTEST2_F(MiMath, givenValueToMakeRightAritmeticShiftWhenUseMiMathThenShiftIsDon
468468
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCB);
469469
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_4);
470470
pAluParam++;
471-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_SAR); // load value to shift to SRCB
471+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeSar); // load value to shift to SRCB
472472
pAluParam->DW0.BitField.Operand1 = 0;
473473
pAluParam->DW0.BitField.Operand2 = 0;
474474
pAluParam++;
@@ -480,7 +480,7 @@ HWTEST2_F(MiMath, givenValueToMakeRightAritmeticShiftWhenUseMiMathThenShiftIsDon
480480
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCB);
481481
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(AluRegisters::R_5);
482482
pAluParam++;
483-
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::OPCODE_SAR); // load value to shift to SRCB
483+
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(NewAluOpcodes::opcodeSar); // load value to shift to SRCB
484484
pAluParam->DW0.BitField.Operand1 = 0;
485485
pAluParam->DW0.BitField.Operand2 = 0;
486486
pAluParam++;

‎opencl/test/unit_test/program/process_elf_binary_tests.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -126,7 +126,7 @@ class ProcessElfBinaryTestsWithBinaryType : public ::testing::TestWithParam<unsi
126126
};
127127

128128
TEST_P(ProcessElfBinaryTestsWithBinaryType, GivenBinaryTypeWhenResolveProgramThenProgramIsProperlyResolved) {
129-
auto mockElf = std::make_unique<MockElfBinaryPatchtokens<enabledIrFormat::ENABLE_SPIRV>>(device->getHardwareInfo());
129+
auto mockElf = std::make_unique<MockElfBinaryPatchtokens<enabledIrFormat::enableSpirv>>(device->getHardwareInfo());
130130
auto pBinary = mockElf->storage;
131131
auto binarySize = mockElf->storage.size();
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@@ -231,4 +231,4 @@ TEST_F(ProcessElfBinaryTests, GivenBinaryWhenIncompatiblePatchtokenVerionThenPro
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cl_int retVal = program->createProgramFromBinary(elfBinary.data(), elfBinary.size(), *device);
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EXPECT_EQ(CL_INVALID_BINARY, retVal);
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}
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}
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}

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