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1 parent 5b6f151 commit 4357712Copy full SHA for 4357712
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -72,7 +72,8 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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}
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bool HasVectorCSR =
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- MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall;
+ MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall &&
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+ Subtarget.hasVInstructions();
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switch (Subtarget.getTargetABI()) {
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default:
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