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Revert "[SLP]Improve costs in computeExtractCost() to avoid crash after D158449."
This caused asserts: Assertion failed: NumElts > 1 && "Expected at least 2-element fixed length vector(s).", file C:\b\s\w\ir\cache\builder\src\third_party\llvm\llvm\lib\Transforms\Vectorize\SLPVectorizer.cpp, line 7096 see comment on llvm@59a67ea > Need to consider the length of the original vector for extractelements, > not the length, matched number of the scalars. It fixes 2 issues: 1) > improves cost estimation; 2) Fixes crashes after D158449. This reverts commit 59a67ea.
1 parent 15b6871 commit 06f3b0e

14 files changed

+476
-484
lines changed

‎llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Lines changed: 21 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -7084,58 +7084,30 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis {
70847084
/// extracted values from \p VL.
70857085
InstructionCost computeExtractCost(ArrayRef<Value *> VL, ArrayRef<int> Mask,
70867086
TTI::ShuffleKind ShuffleKind) {
7087-
unsigned NumElts = 0;
7088-
for (Value *V : VL) {
7089-
auto *EE = dyn_cast<ExtractElementInst>(V);
7090-
if (!EE)
7091-
continue;
7092-
auto *VecTy = cast<FixedVectorType>(EE->getVectorOperandType());
7093-
NumElts = std::max(NumElts, VecTy->getNumElements());
7094-
}
7095-
assert(NumElts > 1 &&
7096-
"Expected at least 2-element fixed length vector(s).");
7097-
auto *VecTy = FixedVectorType::get(VL.front()->getType(), NumElts);
7087+
auto *VecTy = FixedVectorType::get(VL.front()->getType(), VL.size());
70987088
unsigned NumOfParts = TTI.getNumberOfParts(VecTy);
7099-
if (!NumOfParts || NumElts < NumOfParts)
7100-
return TTI.getShuffleCost(ShuffleKind, VecTy, Mask);
7101-
unsigned EltsPerVector = PowerOf2Ceil(divideCeil(NumElts, NumOfParts));
7102-
int ValNum = -1;
7103-
int ValIdx = -1;
7104-
// Check that if trying to permute 2 input vectors (which may result in
7105-
// several vector registers), each per-register subvector is the result of
7106-
// the permutation of 2 single registers.
7107-
if (ShuffleKind != TargetTransformInfo::SK_PermuteSingleSrc &&
7108-
!all_of(enumerate(Mask), [&](auto &&Arg) {
7109-
if (Arg.value() == PoisonMaskElem)
7110-
return true;
7111-
int CurValNum = (Arg.value() % NumElts) / EltsPerVector;
7112-
int CurValIdx = Arg.index() / EltsPerVector;
7113-
if (ValIdx != CurValIdx) {
7114-
ValIdx = CurValIdx;
7115-
ValNum = CurValNum;
7116-
return true;
7117-
}
7118-
return CurValNum == ValNum;
7119-
}))
7089+
7090+
if (ShuffleKind != TargetTransformInfo::SK_PermuteSingleSrc ||
7091+
!NumOfParts || VecTy->getNumElements() < NumOfParts)
71207092
return TTI.getShuffleCost(ShuffleKind, VecTy, Mask);
71217093

7094+
bool AllConsecutive = true;
7095+
unsigned EltsPerVector = VecTy->getNumElements() / NumOfParts;
7096+
unsigned Idx = -1;
71227097
InstructionCost Cost = 0;
71237098

71247099
// Process extracts in blocks of EltsPerVector to check if the source vector
71257100
// operand can be re-used directly. If not, add the cost of creating a
71267101
// shuffle to extract the values into a vector register.
7127-
auto *RegisterVecTy =
7128-
FixedVectorType::get(VL.front()->getType(), EltsPerVector);
71297102
SmallVector<int> RegMask(EltsPerVector, PoisonMaskElem);
7130-
TTI::ShuffleKind RegisterSK = TargetTransformInfo::SK_PermuteSingleSrc;
7131-
Value *VecBase = nullptr;
7132-
bool IsIdentity = true;
7133-
for (auto [Idx, V] : enumerate(VL)) {
7103+
for (auto *V : VL) {
7104+
++Idx;
7105+
71347106
// Reached the start of a new vector registers.
71357107
if (Idx % EltsPerVector == 0) {
71367108
RegMask.assign(EltsPerVector, PoisonMaskElem);
7137-
RegisterSK = TargetTransformInfo::SK_PermuteSingleSrc;
7138-
VecBase = nullptr;
7109+
AllConsecutive = true;
7110+
continue;
71397111
}
71407112

71417113
// Need to exclude undefs from analysis.
@@ -7145,26 +7117,14 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis {
71457117
// Check all extracts for a vector register on the target directly
71467118
// extract values in order.
71477119
unsigned CurrentIdx = *getExtractIndex(cast<Instruction>(V));
7148-
unsigned PrevIdx = CurrentIdx;
7149-
if (Idx % EltsPerVector != 0 && !isa<UndefValue>(VL[Idx - 1]) &&
7150-
Mask[Idx - 1] != PoisonMaskElem)
7151-
PrevIdx = *getExtractIndex(cast<Instruction>(VL[Idx - 1])) + 1;
7152-
if (!VecBase) {
7153-
VecBase = cast<ExtractElementInst>(V)->getVectorOperand();
7154-
RegMask[Idx % EltsPerVector] = CurrentIdx % EltsPerVector;
7155-
IsIdentity = CurrentIdx % EltsPerVector == Idx % EltsPerVector;
7156-
} else if (VecBase != cast<ExtractElementInst>(V)->getVectorOperand()) {
7157-
IsIdentity = false;
7158-
RegisterSK = TargetTransformInfo::SK_PermuteTwoSrc;
7159-
RegMask[Idx % EltsPerVector] =
7160-
CurrentIdx % EltsPerVector + EltsPerVector;
7161-
} else {
7162-
IsIdentity &= PrevIdx == CurrentIdx &&
7163-
CurrentIdx % EltsPerVector == Idx % EltsPerVector;
7120+
if (!isa<UndefValue>(VL[Idx - 1]) && Mask[Idx - 1] != PoisonMaskElem) {
7121+
unsigned PrevIdx = *getExtractIndex(cast<Instruction>(VL[Idx - 1]));
7122+
AllConsecutive &= PrevIdx + 1 == CurrentIdx &&
7123+
CurrentIdx % EltsPerVector == Idx % EltsPerVector;
71647124
RegMask[Idx % EltsPerVector] = CurrentIdx % EltsPerVector;
71657125
}
71667126

7167-
if (IsIdentity)
7127+
if (AllConsecutive)
71687128
continue;
71697129

71707130
// Skip all indices, except for the last index per vector block.
@@ -7174,7 +7134,10 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis {
71747134
// If we have a series of extracts which are not consecutive and hence
71757135
// cannot re-use the source vector register directly, compute the shuffle
71767136
// cost to extract the vector with EltsPerVector elements.
7177-
Cost += TTI.getShuffleCost(RegisterSK, RegisterVecTy, RegMask);
7137+
Cost += TTI.getShuffleCost(
7138+
TargetTransformInfo::SK_PermuteSingleSrc,
7139+
FixedVectorType::get(VecTy->getElementType(), EltsPerVector),
7140+
RegMask);
71787141
}
71797142
return Cost;
71807143
}

‎llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -291,19 +291,14 @@ define <4 x i16> @uadd_sat_v4i16(<4 x i16> %arg0, <4 x i16> %arg1) {
291291
;
292292
; GFX8-LABEL: @uadd_sat_v4i16(
293293
; GFX8-NEXT: bb:
294-
; GFX8-NEXT: [[ARG0_2:%.*]] = extractelement <4 x i16> [[ARG0:%.*]], i64 2
295-
; GFX8-NEXT: [[ARG0_3:%.*]] = extractelement <4 x i16> [[ARG0]], i64 3
296-
; GFX8-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i16> [[ARG1:%.*]], i64 2
297-
; GFX8-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i16> [[ARG1]], i64 3
298-
; GFX8-NEXT: [[TMP0:%.*]] = shufflevector <4 x i16> [[ARG0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
299-
; GFX8-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[ARG1]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
294+
; GFX8-NEXT: [[TMP0:%.*]] = shufflevector <4 x i16> [[ARG0:%.*]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
295+
; GFX8-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[ARG1:%.*]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
300296
; GFX8-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
301-
; GFX8-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
302-
; GFX8-NEXT: [[ADD_3:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_3]], i16 [[ARG1_3]])
303-
; GFX8-NEXT: [[TMP3:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
304-
; GFX8-NEXT: [[INS_2:%.*]] = insertelement <4 x i16> [[TMP3]], i16 [[ADD_2]], i64 2
305-
; GFX8-NEXT: [[INS_3:%.*]] = insertelement <4 x i16> [[INS_2]], i16 [[ADD_3]], i64 3
306-
; GFX8-NEXT: ret <4 x i16> [[INS_3]]
297+
; GFX8-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[ARG0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
298+
; GFX8-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[ARG1]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
299+
; GFX8-NEXT: [[TMP5:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP3]], <2 x i16> [[TMP4]])
300+
; GFX8-NEXT: [[INS_31:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
301+
; GFX8-NEXT: ret <4 x i16> [[INS_31]]
307302
;
308303
bb:
309304
%arg0.0 = extractelement <4 x i16> %arg0, i64 0

‎llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -291,19 +291,14 @@ define <4 x i16> @uadd_sat_v4i16(<4 x i16> %arg0, <4 x i16> %arg1) {
291291
;
292292
; GFX8-LABEL: @uadd_sat_v4i16(
293293
; GFX8-NEXT: bb:
294-
; GFX8-NEXT: [[ARG0_2:%.*]] = extractelement <4 x i16> [[ARG0:%.*]], i64 2
295-
; GFX8-NEXT: [[ARG0_3:%.*]] = extractelement <4 x i16> [[ARG0]], i64 3
296-
; GFX8-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i16> [[ARG1:%.*]], i64 2
297-
; GFX8-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i16> [[ARG1]], i64 3
298-
; GFX8-NEXT: [[TMP0:%.*]] = shufflevector <4 x i16> [[ARG0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
299-
; GFX8-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[ARG1]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
294+
; GFX8-NEXT: [[TMP0:%.*]] = shufflevector <4 x i16> [[ARG0:%.*]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
295+
; GFX8-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[ARG1:%.*]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
300296
; GFX8-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
301-
; GFX8-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
302-
; GFX8-NEXT: [[ADD_3:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_3]], i16 [[ARG1_3]])
303-
; GFX8-NEXT: [[TMP3:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
304-
; GFX8-NEXT: [[INS_2:%.*]] = insertelement <4 x i16> [[TMP3]], i16 [[ADD_2]], i64 2
305-
; GFX8-NEXT: [[INS_3:%.*]] = insertelement <4 x i16> [[INS_2]], i16 [[ADD_3]], i64 3
306-
; GFX8-NEXT: ret <4 x i16> [[INS_3]]
297+
; GFX8-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[ARG0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
298+
; GFX8-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[ARG1]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
299+
; GFX8-NEXT: [[TMP5:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP3]], <2 x i16> [[TMP4]])
300+
; GFX8-NEXT: [[INS_31:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
301+
; GFX8-NEXT: ret <4 x i16> [[INS_31]]
307302
;
308303
bb:
309304
%arg0.0 = extractelement <4 x i16> %arg0, i64 0

‎llvm/test/Transforms/SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -4,15 +4,10 @@
44
define <2 x i16> @uadd_sat_v9i16_combine_vi16(<9 x i16> %arg0, <9 x i16> %arg1) {
55
; CHECK-LABEL: @uadd_sat_v9i16_combine_vi16(
66
; CHECK-NEXT: bb:
7-
; CHECK-NEXT: [[ARG0_1:%.*]] = extractelement <9 x i16> undef, i64 7
8-
; CHECK-NEXT: [[ARG0_2:%.*]] = extractelement <9 x i16> [[ARG0:%.*]], i64 8
9-
; CHECK-NEXT: [[ARG1_1:%.*]] = extractelement <9 x i16> [[ARG1:%.*]], i64 7
10-
; CHECK-NEXT: [[ARG1_2:%.*]] = extractelement <9 x i16> [[ARG1]], i64 8
11-
; CHECK-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
12-
; CHECK-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
13-
; CHECK-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> undef, i16 [[ADD_1]], i64 0
14-
; CHECK-NEXT: [[INS_2:%.*]] = insertelement <2 x i16> [[INS_1]], i16 [[ADD_2]], i64 1
15-
; CHECK-NEXT: ret <2 x i16> [[INS_2]]
7+
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x i16> [[ARG0:%.*]], <9 x i16> poison, <2 x i32> <i32 poison, i32 8>
8+
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <9 x i16> [[ARG1:%.*]], <9 x i16> poison, <2 x i32> <i32 7, i32 8>
9+
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
10+
; CHECK-NEXT: ret <2 x i16> [[TMP2]]
1611
;
1712
bb:
1813
%arg0.1 = extractelement <9 x i16> undef, i64 7

‎llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll

Lines changed: 20 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -4,23 +4,20 @@
44
define <4 x half> @phis(i1 %cmp1, <4 x half> %in1, <4 x half> %in2) {
55
; CHECK-LABEL: @phis(
66
; CHECK-NEXT: entry:
7-
; CHECK-NEXT: [[A2:%.*]] = extractelement <4 x half> [[IN1:%.*]], i64 2
8-
; CHECK-NEXT: [[A3:%.*]] = extractelement <4 x half> [[IN1]], i64 3
9-
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x half> [[IN1]], <4 x half> poison, <2 x i32> <i32 0, i32 1>
7+
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x half> [[IN1:%.*]], <4 x half> poison, <2 x i32> <i32 0, i32 1>
8+
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x half> [[IN1]], <4 x half> poison, <2 x i32> <i32 2, i32 3>
109
; CHECK-NEXT: br i1 [[CMP1:%.*]], label [[BB1:%.*]], label [[BB0:%.*]]
1110
; CHECK: bb0:
12-
; CHECK-NEXT: [[B2:%.*]] = extractelement <4 x half> [[IN2:%.*]], i64 2
13-
; CHECK-NEXT: [[B3:%.*]] = extractelement <4 x half> [[IN2]], i64 3
14-
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x half> [[IN2]], <4 x half> poison, <2 x i32> <i32 0, i32 1>
11+
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x half> [[IN2:%.*]], <4 x half> poison, <2 x i32> <i32 0, i32 1>
12+
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x half> [[IN2]], <4 x half> poison, <2 x i32> <i32 2, i32 3>
1513
; CHECK-NEXT: br label [[BB1]]
1614
; CHECK: bb1:
17-
; CHECK-NEXT: [[C2:%.*]] = phi half [ [[A2]], [[ENTRY:%.*]] ], [ [[B2]], [[BB0]] ]
18-
; CHECK-NEXT: [[C3:%.*]] = phi half [ [[A3]], [[ENTRY]] ], [ [[B3]], [[BB0]] ]
19-
; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x half> [ [[TMP0]], [[ENTRY]] ], [ [[TMP1]], [[BB0]] ]
20-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x half> [[TMP2]], <2 x half> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
21-
; CHECK-NEXT: [[O2:%.*]] = insertelement <4 x half> [[TMP3]], half [[C2]], i64 2
22-
; CHECK-NEXT: [[O3:%.*]] = insertelement <4 x half> [[O2]], half [[C3]], i64 3
23-
; CHECK-NEXT: ret <4 x half> [[O3]]
15+
; CHECK-NEXT: [[TMP4:%.*]] = phi <2 x half> [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP2]], [[BB0]] ]
16+
; CHECK-NEXT: [[TMP5:%.*]] = phi <2 x half> [ [[TMP1]], [[ENTRY]] ], [ [[TMP3]], [[BB0]] ]
17+
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x half> [[TMP4]], <2 x half> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
18+
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x half> [[TMP5]], <2 x half> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
19+
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x half> [[TMP4]], <2 x half> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
20+
; CHECK-NEXT: ret <4 x half> [[TMP8]]
2421
;
2522
entry:
2623
%a0 = extractelement <4 x half> %in1, i64 0
@@ -52,23 +49,20 @@ bb1:
5249
define <4 x half> @phis_reverse(i1 %cmp1, <4 x half> %in1, <4 x half> %in2) {
5350
; CHECK-LABEL: @phis_reverse(
5451
; CHECK-NEXT: entry:
55-
; CHECK-NEXT: [[A2:%.*]] = extractelement <4 x half> [[IN1:%.*]], i64 2
56-
; CHECK-NEXT: [[A3:%.*]] = extractelement <4 x half> [[IN1]], i64 3
57-
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x half> [[IN1]], <4 x half> poison, <2 x i32> <i32 0, i32 1>
52+
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x half> [[IN1:%.*]], <4 x half> poison, <2 x i32> <i32 2, i32 3>
53+
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x half> [[IN1]], <4 x half> poison, <2 x i32> <i32 0, i32 1>
5854
; CHECK-NEXT: br i1 [[CMP1:%.*]], label [[BB1:%.*]], label [[BB0:%.*]]
5955
; CHECK: bb0:
60-
; CHECK-NEXT: [[B2:%.*]] = extractelement <4 x half> [[IN2:%.*]], i64 2
61-
; CHECK-NEXT: [[B3:%.*]] = extractelement <4 x half> [[IN2]], i64 3
62-
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x half> [[IN2]], <4 x half> poison, <2 x i32> <i32 0, i32 1>
56+
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x half> [[IN2:%.*]], <4 x half> poison, <2 x i32> <i32 2, i32 3>
57+
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x half> [[IN2]], <4 x half> poison, <2 x i32> <i32 0, i32 1>
6358
; CHECK-NEXT: br label [[BB1]]
6459
; CHECK: bb1:
65-
; CHECK-NEXT: [[C3:%.*]] = phi half [ [[A3]], [[ENTRY:%.*]] ], [ [[B3]], [[BB0]] ]
66-
; CHECK-NEXT: [[C2:%.*]] = phi half [ [[A2]], [[ENTRY]] ], [ [[B2]], [[BB0]] ]
67-
; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x half> [ [[TMP0]], [[ENTRY]] ], [ [[TMP1]], [[BB0]] ]
68-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x half> [[TMP2]], <2 x half> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
69-
; CHECK-NEXT: [[O2:%.*]] = insertelement <4 x half> [[TMP3]], half [[C2]], i64 2
70-
; CHECK-NEXT: [[O3:%.*]] = insertelement <4 x half> [[O2]], half [[C3]], i64 3
71-
; CHECK-NEXT: ret <4 x half> [[O3]]
60+
; CHECK-NEXT: [[TMP4:%.*]] = phi <2 x half> [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP2]], [[BB0]] ]
61+
; CHECK-NEXT: [[TMP5:%.*]] = phi <2 x half> [ [[TMP1]], [[ENTRY]] ], [ [[TMP3]], [[BB0]] ]
62+
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x half> [[TMP5]], <2 x half> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
63+
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x half> [[TMP4]], <2 x half> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
64+
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x half> [[TMP6]], <4 x half> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
65+
; CHECK-NEXT: ret <4 x half> [[TMP8]]
7266
;
7367
entry:
7468
%a0 = extractelement <4 x half> %in1, i64 0

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