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klensy
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fixes moved from llvm#91854 
1 parent 3bcccb6 commit fb1dd1b

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lines changed

‎llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ define void @broadcast() #0{
3131
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
3232
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
3333
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
34-
; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction: ret void
34+
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
3535

3636
%zero = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
3737
%1 = shufflevector <vscale x 32 x i8> undef, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer

‎llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ S:
9090
br i1 %cond.uni, label %exit, label %T
9191

9292
T:
93-
; CHECK-NIT: DIVERGENT: %tt.phi = phi i32
93+
; CHECK-NOT: DIVERGENT: %tt.phi = phi i32
9494
%tt.phi = phi i32 [ %ss, %S ], [ %a, %entry ]
9595
%tt = add i32 %b, 1
9696
br label %P

‎llvm/test/Assembler/bfloat.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,25 +37,25 @@ define float @check_bfloat_convert() {
3737
ret float %tmp
3838
}
3939

40-
; ASSEM-DISASS-LABEL @snan_bfloat
40+
; ASSEM-DISASS-LABEL: @snan_bfloat
4141
define bfloat @snan_bfloat() {
4242
; ASSEM-DISASS: ret bfloat 0xR7F81
4343
ret bfloat 0xR7F81
4444
}
4545

46-
; ASSEM-DISASS-LABEL @qnan_bfloat
46+
; ASSEM-DISASS-LABEL: @qnan_bfloat
4747
define bfloat @qnan_bfloat() {
4848
; ASSEM-DISASS: ret bfloat 0xR7FC0
4949
ret bfloat 0xR7FC0
5050
}
5151

52-
; ASSEM-DISASS-LABEL @pos_inf_bfloat
52+
; ASSEM-DISASS-LABEL: @pos_inf_bfloat
5353
define bfloat @pos_inf_bfloat() {
5454
; ASSEM-DISASS: ret bfloat 0xR7F80
5555
ret bfloat 0xR7F80
5656
}
5757

58-
; ASSEM-DISASS-LABEL @neg_inf_bfloat
58+
; ASSEM-DISASS-LABEL: @neg_inf_bfloat
5959
define bfloat @neg_inf_bfloat() {
6060
; ASSEM-DISASS: ret bfloat 0xRFF80
6161
ret bfloat 0xRFF80

‎llvm/test/CodeGen/AArch64/arm64_32-atomics.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2,70 +2,70 @@
22
; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
33

44
define i8 @test_load_8(ptr %addr) {
5-
; CHECK-LABAL: test_load_8:
5+
; CHECK-LABEL: test_load_8:
66
; CHECK: ldarb w0, [x0]
77
%val = load atomic i8, ptr %addr seq_cst, align 1
88
ret i8 %val
99
}
1010

1111
define i16 @test_load_16(ptr %addr) {
12-
; CHECK-LABAL: test_load_16:
12+
; CHECK-LABEL: test_load_16:
1313
; CHECK: ldarh w0, [x0]
1414
%val = load atomic i16, ptr %addr acquire, align 2
1515
ret i16 %val
1616
}
1717

1818
define i32 @test_load_32(ptr %addr) {
19-
; CHECK-LABAL: test_load_32:
19+
; CHECK-LABEL: test_load_32:
2020
; CHECK: ldar w0, [x0]
2121
%val = load atomic i32, ptr %addr seq_cst, align 4
2222
ret i32 %val
2323
}
2424

2525
define i64 @test_load_64(ptr %addr) {
26-
; CHECK-LABAL: test_load_64:
26+
; CHECK-LABEL: test_load_64:
2727
; CHECK: ldar x0, [x0]
2828
%val = load atomic i64, ptr %addr seq_cst, align 8
2929
ret i64 %val
3030
}
3131

3232
define ptr @test_load_ptr(ptr %addr) {
33-
; CHECK-LABAL: test_load_ptr:
33+
; CHECK-LABEL: test_load_ptr:
3434
; CHECK: ldar w0, [x0]
3535
%val = load atomic ptr, ptr %addr seq_cst, align 8
3636
ret ptr %val
3737
}
3838

3939
define void @test_store_8(ptr %addr) {
40-
; CHECK-LABAL: test_store_8:
40+
; CHECK-LABEL: test_store_8:
4141
; CHECK: stlrb wzr, [x0]
4242
store atomic i8 0, ptr %addr seq_cst, align 1
4343
ret void
4444
}
4545

4646
define void @test_store_16(ptr %addr) {
47-
; CHECK-LABAL: test_store_16:
47+
; CHECK-LABEL: test_store_16:
4848
; CHECK: stlrh wzr, [x0]
4949
store atomic i16 0, ptr %addr seq_cst, align 2
5050
ret void
5151
}
5252

5353
define void @test_store_32(ptr %addr) {
54-
; CHECK-LABAL: test_store_32:
54+
; CHECK-LABEL: test_store_32:
5555
; CHECK: stlr wzr, [x0]
5656
store atomic i32 0, ptr %addr seq_cst, align 4
5757
ret void
5858
}
5959

6060
define void @test_store_64(ptr %addr) {
61-
; CHECK-LABAL: test_store_64:
61+
; CHECK-LABEL: test_store_64:
6262
; CHECK: stlr xzr, [x0]
6363
store atomic i64 0, ptr %addr seq_cst, align 8
6464
ret void
6565
}
6666

6767
define void @test_store_ptr(ptr %addr) {
68-
; CHECK-LABAL: test_store_ptr:
68+
; CHECK-LABEL: test_store_ptr:
6969
; CHECK: stlr wzr, [x0]
7070
store atomic ptr null, ptr %addr seq_cst, align 8
7171
ret void

‎llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s
22

33
define void @no_op() nounwind {
4-
; CHECK-LABEL .def $ientry_thunk$cdecl$v$v;
4+
; CHECK-LABEL: .def $ientry_thunk$cdecl$v$v;
55
; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$v$v
66
; CHECK: // %bb.0:
77
; CHECK-NEXT: stp q6, q7, [sp, #-176]! // 32-byte Folded Spill

‎llvm/test/CodeGen/AArch64/fpimm.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ define void @check_double() {
3838
; 64-bit ORR followed by MOVK.
3939
; CHECK-DAG: mov [[XFP0:x[0-9]+]], #1082331758844
4040
; CHECK-DAG: movk [[XFP0]], #64764, lsl #16
41-
; CHECk-DAG: fmov {{d[0-9]+}}, [[XFP0]]
41+
; CHECK-DAG: fmov {{d[0-9]+}}, [[XFP0]]
4242
%newval3 = fadd double %val, 0xFCFCFC00FC
4343
store volatile double %newval3, ptr @varf64
4444

‎llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" {
2828
}
2929

3030
define void @b() "sign-return-address"="non-leaf" {
31-
; CHECK-LABE: b: // @b
31+
; CHECK-LABEL: b: // @b
3232
; V8A-NOT: hint #25
3333
; V83A-NOT: paciasp
3434
; CHECK-NOT: .cfi_negate_ra_state

‎llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -192,7 +192,7 @@ entry:
192192
; CHECK: .Lfunc_end
193193
}
194194

195-
; HARDEN-label: __llvm_slsblr_thunk_x0:
195+
; HARDEN-LABEL: __llvm_slsblr_thunk_x0:
196196
; HARDEN: mov x16, x0
197197
; HARDEN: br x16
198198
; ISBDSB-NEXT: dsb sy
@@ -208,7 +208,7 @@ entry:
208208
; HARDEN-COMDAT-OFF-NOT: .hidden __llvm_slsblr_thunk_x19
209209
; HARDEN-COMDAT-OFF-NOT: .weak __llvm_slsblr_thunk_x19
210210
; HARDEN-COMDAT-OFF: .type __llvm_slsblr_thunk_x19,@function
211-
; HARDEN-label: __llvm_slsblr_thunk_x19:
211+
; HARDEN-LABEL: __llvm_slsblr_thunk_x19:
212212
; HARDEN: mov x16, x19
213213
; HARDEN: br x16
214214
; ISBDSB-NEXT: dsb sy

‎llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212

1313
# This test also checks that pairwise store STP is generated.
1414

15-
# CHECK-LABLE: test
15+
# CHECK-LABEL: test
1616
# CHECK: bb.0:
1717
# CHECK-NEXT: liveins: $x0, $x17, $x18
1818
# CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)

‎llvm/test/CodeGen/AMDGPU/addrspacecast.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %pt
108108
}
109109

110110
; no-op
111-
; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
111+
; HSA-LABEL: {{^}}use_constant_to_flat_addrspacecast:
112112
; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
113113
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
114114
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
@@ -119,7 +119,7 @@ define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %
119119
ret void
120120
}
121121

122-
; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
122+
; HSA-LABEL: {{^}}use_constant_to_global_addrspacecast:
123123
; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
124124
; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
125125
; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]

‎llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44

55
---
66

7-
# GCN-label: name: vop3
7+
# GCN-LABEL: name: vop3
88
# GCN: %6:vgpr_32, %7:sreg_32_xm0_xexec = V_SUBBREV_U32_e64_dpp %3, %0, %1, %5, 1, 1, 15, 15, 1, implicit $exec
99
# GCN: %8:vgpr_32 = V_CVT_PK_U8_F32_e64_dpp %3, 4, %0, 2, %2, 2, %1, 1, 1, 15, 15, 1, implicit $mode, implicit $exec
1010
# GCN: %10:vgpr_32 = V_MED3_F32_e64 0, %9, 0, %0, 0, 12345678, 0, 0, implicit $mode, implicit $exec
@@ -37,7 +37,7 @@ body: |
3737
...
3838
---
3939

40-
# GCN-label: name: vop3_sgpr_src1
40+
# GCN-LABEL: name: vop3_sgpr_src1
4141
# GCN: %6:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %1, 0, %2, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
4242
# GFX1100: %8:vgpr_32 = V_MED3_F32_e64 0, %7, 0, %2, 0, %1, 0, 0, implicit $mode, implicit $exec
4343
# GFX1150: %8:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %2, 0, %1, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
@@ -81,7 +81,7 @@ body: |
8181
---
8282

8383
# Regression test for src_modifiers on base u16 opcode
84-
# GCN-label: name: vop3_u16
84+
# GCN-LABEL: name: vop3_u16
8585
# GCN: %5:vgpr_32 = V_ADD_NC_U16_e64_dpp %3, 0, %1, 0, %3, 0, 0, 1, 15, 15, 1, implicit $exec
8686
# GCN: %7:vgpr_32 = V_ADD_NC_U16_e64_dpp %3, 1, %5, 2, %5, 0, 0, 1, 15, 15, 1, implicit $exec
8787
# GCN: %9:vgpr_32 = V_ADD_NC_U16_e64 4, %8, 8, %7, 0, 0, implicit $exec
@@ -205,7 +205,7 @@ body: |
205205
...
206206

207207
# do not combine, dpp arg used twice
208-
# GCN-label: name: dpp_arg_twice
208+
# GCN-LABEL: name: dpp_arg_twice
209209
# GCN: %4:vgpr_32 = V_FMA_F32_e64 1, %1, 2, %3, 2, %3, 1, 2, implicit $mode, implicit $exec
210210
# GCN: %6:vgpr_32 = V_FMA_F32_e64 2, %5, 2, %1, 2, %5, 1, 2, implicit $mode, implicit $exec
211211
# GCN: %8:vgpr_32 = V_FMA_F32_e64 2, %7, 2, %7, 2, %1, 1, 2, implicit $mode, implicit $exec
@@ -231,7 +231,7 @@ body: |
231231
...
232232

233233
# when the dpp source isn't a src0 operand the operation should be commuted if possible
234-
# GCN-label: name: dpp_commute_e64
234+
# GCN-LABEL: name: dpp_commute_e64
235235
# GCN: %4:vgpr_32 = V_MUL_U32_U24_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec
236236
# GCN: %7:vgpr_32 = V_FMA_F32_e64_dpp %5, 2, %0, 1, %1, 2, %1, 1, 2, 1, 15, 15, 1, implicit $mode, implicit $exec
237237
# GCN: %10:vgpr_32 = V_SUBREV_U32_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec

‎llvm/test/CodeGen/ARM/dsp-loop-indexing.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
; CHECK-DEFAULT: ldr{{.*}}, #4]
2323
; CHECK-DEFAULT: str{{.*}}, #4]
2424
; CHECK-DEFAULT: ldr{{.*}}, #8]!
25-
; CHECK-DEAFULT: ldr{{.*}}, #8]!
25+
; CHECK-DEFAULT: ldr{{.*}}, #8]!
2626
; CHECK-DEFAULT: str{{.*}}, #8]!
2727

2828
; CHECK-COMPLEX: ldr{{.*}}, #8]!

‎llvm/test/CodeGen/ARM/shifter_operand.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,6 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) {
121121
; CHECK-THUMB-NEXT: orrs r0, r1
122122
; CHECK-THUMB-NEXT: bx lr
123123
entry:
124-
; CHECk-THUMB: orrs r0, r1
125124
%mul = mul i32 %y, 63767
126125
%or = or i32 %mul, %x
127126
ret i32 %or

‎llvm/test/CodeGen/ARM/speculation-hardening-sls.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -248,7 +248,7 @@ entry:
248248
; HARDEN-COMDAT-OFF-NOT: .hidden {{__llvm_slsblr_thunk_(arm|thumb)_r5}}
249249
; HARDEN-COMDAT-OFF-NOT: .weak {{__llvm_slsblr_thunk_(arm|thumb)_r5}}
250250
; HARDEN-COMDAT-OFF: .type {{__llvm_slsblr_thunk_(arm|thumb)_r5}},%function
251-
; HARDEN-label: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}:
251+
; HARDEN-LABEL: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}:
252252
; HARDEN: bx r5
253253
; ISBDSB-NEXT: dsb sy
254254
; ISBDSB-NEXT: isb

‎llvm/test/CodeGen/ARM/sxt_rot.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,6 @@ define signext i8 @test1(i32 %A) {
2222
; CHECK-V7: @ %bb.0:
2323
; CHECK-V7-NEXT: sbfx r0, r0, #8, #8
2424
; CHECK-V7-NEXT: bx lr
25-
; CHECk-V7: sbfx r0, r0, #8, #8
2625
%B = lshr i32 %A, 8
2726
%C = shl i32 %A, 24
2827
%D = or i32 %B, %C

‎llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,11 @@
33
; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64
44

55
define i32 @shl_32(i32 %a, i32 %b) {
6-
; MIPS32-LABLE: shl_32:
6+
; MIPS32-LABEL: shl_32:
77
; MIPS32: # %bb.0:
88
; MIPS32-NEXT: jr $ra
99
; MIPS32-NEXT: sllv $2, $4, $5
10-
; MIPS64-LABLE: shl_32:
10+
; MIPS64-LABEL: shl_32:
1111
; MIPS64: # %bb.0:
1212
; MIPS64-NEXT: sll $1, $5, 0
1313
; MIPS64-NEXT: sll $2, $4, 0
@@ -19,11 +19,11 @@ define i32 @shl_32(i32 %a, i32 %b) {
1919
}
2020

2121
define i32 @lshr_32(i32 %a, i32 %b) {
22-
; MIPS32-LABLE: lshr_32:
22+
; MIPS32-LABEL: lshr_32:
2323
; MIPS32: # %bb.0:
2424
; MIPS32-NEXT: jr $ra
2525
; MIPS32-NEXT: srlv $2, $4, $5
26-
; MIPS64-LABLE: lshr_32:
26+
; MIPS64-LABEL: lshr_32:
2727
; MIPS64: # %bb.0:
2828
; MIPS64-NEXT: sll $1, $5, 0
2929
; MIPS64-NEXT: sll $2, $4, 0
@@ -35,11 +35,11 @@ define i32 @lshr_32(i32 %a, i32 %b) {
3535
}
3636

3737
define i32 @ashr_32(i32 %a, i32 %b) {
38-
; MIPS32-LABLE: ashr_32:
38+
; MIPS32-LABEL: ashr_32:
3939
; MIPS32: # %bb.0:
4040
; MIPS32-NEXT: jr $ra
4141
; MIPS32-NEXT: srav $2, $4, $5
42-
; MIPS64-LABLE: ashr_32:
42+
; MIPS64-LABEL: ashr_32:
4343
; MIPS64: # %bb.0:
4444
; MIPS64-NEXT: sll $1, $5, 0
4545
; MIPS64-NEXT: sll $2, $4, 0
@@ -51,7 +51,7 @@ define i32 @ashr_32(i32 %a, i32 %b) {
5151
}
5252

5353
define i64 @shl_64(i64 %a, i64 %b) {
54-
; MIPS64-LABLE: shl_64:
54+
; MIPS64-LABEL: shl_64:
5555
; MIPS64: # %bb.0:
5656
; MIPS64-NEXT: sll $1, $5, 0
5757
; MIPS64-NEXT: jr $ra
@@ -62,7 +62,7 @@ define i64 @shl_64(i64 %a, i64 %b) {
6262
}
6363

6464
define i64 @lshr_64(i64 %a, i64 %b) {
65-
; MIPS64-LABLE: lshr_64:
65+
; MIPS64-LABEL: lshr_64:
6666
; MIPS64: # %bb.0:
6767
; MIPS64-NEXT: sll $1, $5, 0
6868
; MIPS64-NEXT: jr $ra
@@ -73,7 +73,7 @@ define i64 @lshr_64(i64 %a, i64 %b) {
7373
}
7474

7575
define i64 @ashr_64(i64 %a, i64 %b) {
76-
; MIPS64-LABLE: ashr_64:
76+
; MIPS64-LABEL: ashr_64:
7777
; MIPS64: # %bb.0:
7878
; MIPS64-NEXT: sll $1, $5, 0
7979
; MIPS64-NEXT: jr $ra

‎llvm/test/CodeGen/NVPTX/idioms.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ define %struct.S16 @i32_to_2xi16(i32 noundef %in) {
4242
%high = trunc i32 %high32 to i16
4343
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_param_0];
4444
; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]];
45-
; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
45+
; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
4646
%s1 = insertvalue %struct.S16 poison, i16 %low, 0
4747
%s = insertvalue %struct.S16 %s1, i16 %high, 1
4848
ret %struct.S16 %s
@@ -56,7 +56,7 @@ define %struct.S16 @i32_to_2xi16_lh(i32 noundef %in) {
5656
%low = trunc i32 %in to i16
5757
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_lh_param_0];
5858
; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]];
59-
; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
59+
; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
6060
%s1 = insertvalue %struct.S16 poison, i16 %low, 0
6161
%s = insertvalue %struct.S16 %s1, i16 %high, 1
6262
ret %struct.S16 %s
@@ -84,7 +84,7 @@ define %struct.S32 @i64_to_2xi32(i64 noundef %in) {
8484
%high = trunc i64 %high64 to i32
8585
; CHECK: ld.param.u64 %[[R64:rd[0-9]+]], [i64_to_2xi32_param_0];
8686
; CHECK-DAG: cvt.u32.u64 %r{{[0-9+]}}, %[[R64]];
87-
; CHECK-DAG mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]];
87+
; CHECK-DAG: mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]];
8888
%s1 = insertvalue %struct.S32 poison, i32 %low, 0
8989
%s = insertvalue %struct.S32 %s1, i32 %high, 1
9090
ret %struct.S32 %s
@@ -114,8 +114,8 @@ define %struct.S16 @i32_to_2xi16_shr(i32 noundef %i){
114114
%h = trunc i32 %h32 to i16
115115
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_shr_param_0];
116116
; CHECK: shr.s32 %[[R32H:r[0-9]+]], %[[R32]], 16;
117-
; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
118-
; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]];
117+
; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
118+
; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]];
119119
%s0 = insertvalue %struct.S16 poison, i16 %l, 0
120120
%s1 = insertvalue %struct.S16 %s0, i16 %h, 1
121121
ret %struct.S16 %s1

‎llvm/test/CodeGen/SPARC/inlineasm.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ entry:
144144
ret void
145145
}
146146

147-
; CHECK-label:test_twinword
147+
; CHECK-LABEL:test_twinword
148148
; CHECK: rd %asr5, %i1
149149
; CHECK: srlx %i1, 32, %i0
150150

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