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[BOLT][Instrumentation] Initial instrumentation support for RISCV64 (llvm#133882)
This patch adds code generation for RISCV64 instrumentation.The work involved includes the following three points: a) Implements support for instrumenting direct function call and jump on RISC-V which relies on , Atomic instructions (used to increment counters) are only available on RISC-V when the A extension is used. b) Implements support for instrumenting direct function inderect call by implementing the createInstrumentedIndCallHandlerEntryBB and createInstrumentedIndCallHandlerExitBB interfaces. In this process, we need to accurately record the target address and IndCallID to ensure the correct recording of the indirect call counters. c)Implemented the RISCV64 Bolt runtime library, implemented some system call interfaces through embedded assembly. Get the difference between runtime addrress of .text section andstatic address in section header table, which in turn can be used to search for indirect call description. However, the community code currently has problems with relocation in some scenarios, but this has nothing to do with instrumentation. We may continue to submit patches to fix the related bugs.
1 parent 9c12064 commit 2147e46

11 files changed

+984
-11
lines changed

bolt/CMakeLists.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,8 @@ endforeach()
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set(BOLT_ENABLE_RUNTIME_default OFF)
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if ((CMAKE_SYSTEM_PROCESSOR STREQUAL "x86_64"
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OR CMAKE_SYSTEM_PROCESSOR MATCHES "^(arm64|aarch64)$")
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OR CMAKE_SYSTEM_PROCESSOR MATCHES "^(arm64|aarch64)$"
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OR CMAKE_SYSTEM_PROCESSOR STREQUAL "riscv64")
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AND (CMAKE_SYSTEM_NAME STREQUAL "Linux"
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OR CMAKE_SYSTEM_NAME STREQUAL "Darwin")
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AND (NOT CMAKE_CROSSCOMPILING))

bolt/lib/Core/Relocation.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,7 @@ static bool isSupportedRISCV(uint32_t Type) {
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case ELF::R_RISCV_LO12_S:
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case ELF::R_RISCV_64:
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case ELF::R_RISCV_TLS_GOT_HI20:
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case ELF::R_RISCV_TLS_GD_HI20:
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case ELF::R_RISCV_TPREL_HI20:
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case ELF::R_RISCV_TPREL_ADD:
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case ELF::R_RISCV_TPREL_LO12_I:
@@ -236,6 +237,7 @@ static size_t getSizeForTypeRISCV(uint32_t Type) {
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case ELF::R_RISCV_64:
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case ELF::R_RISCV_GOT_HI20:
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case ELF::R_RISCV_TLS_GOT_HI20:
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case ELF::R_RISCV_TLS_GD_HI20:
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// See extractValueRISCV for why this is necessary.
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return 8;
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}
@@ -491,6 +493,7 @@ static uint64_t extractValueRISCV(uint32_t Type, uint64_t Contents,
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return extractBImmRISCV(Contents);
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case ELF::R_RISCV_GOT_HI20:
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case ELF::R_RISCV_TLS_GOT_HI20:
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case ELF::R_RISCV_TLS_GD_HI20:
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// We need to know the exact address of the GOT entry so we extract the
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// value from both the AUIPC and L[D|W]. We cannot rely on the symbol in the
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// relocation for this since it simply refers to the object that is stored
@@ -707,6 +710,7 @@ static bool isPCRelativeRISCV(uint32_t Type) {
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case ELF::R_RISCV_RVC_BRANCH:
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case ELF::R_RISCV_32_PCREL:
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case ELF::R_RISCV_TLS_GOT_HI20:
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case ELF::R_RISCV_TLS_GD_HI20:
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return true;
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}
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}

bolt/lib/Rewrite/RewriteInstance.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2926,12 +2926,12 @@ void RewriteInstance::handleRelocation(const SectionRef &RelocatedSection,
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if (BinaryData *BD = BC->getBinaryDataContainingAddress(SymbolAddress)) {
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// Note: this assertion is trying to check sanity of BinaryData objects
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// but AArch64 has inferred and incomplete object locations coming from
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// GOT/TLS or any other non-trivial relocation (that requires creation
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// of sections and whose symbol address is not really what should be
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// encoded in the instruction). So we essentially disabled this check
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// but AArch64 and RISCV has inferred and incomplete object locations
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// coming from GOT/TLS or any other non-trivial relocation (that requires
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// creation of sections and whose symbol address is not really what should
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// be encoded in the instruction). So we essentially disabled this check
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// for AArch64 and live with bogus names for objects.
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assert((IsAArch64 || IsSectionRelocation ||
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assert((IsAArch64 || BC->isRISCV() || IsSectionRelocation ||
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BD->nameStartsWith(SymbolName) ||
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BD->nameStartsWith("PG" + SymbolName) ||
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(BD->nameStartsWith("ANONYMOUS") &&

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