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[HEXAGON] Fix corner cases for hwloops pass (llvm#135439)
Add check to make sure Dist > 0 or Dist < 0 for appropriate cmp cases to hexagon hardware loops pass. The change modifies the HexagonHardwareLoops pass to add runtime checks to make sure that end_value > initial_value for less than comparisons and end_value < initial_value for greater than comparisons. Fix for llvm#133241 @androm3da @iajbar PTAL --------- Co-authored-by: aankit-quic <[email protected]>
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lines changed

3 files changed

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‎llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

Lines changed: 45 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -725,6 +725,11 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
725725
Register IVReg,
726726
int64_t IVBump,
727727
Comparison::Kind Cmp) const {
728+
LLVM_DEBUG(llvm::dbgs() << "Loop: " << *Loop << "\n");
729+
LLVM_DEBUG(llvm::dbgs() << "Initial Value: " << *Start << "\n");
730+
LLVM_DEBUG(llvm::dbgs() << "End Value: " << *End << "\n");
731+
LLVM_DEBUG(llvm::dbgs() << "Inc/Dec Value: " << IVBump << "\n");
732+
LLVM_DEBUG(llvm::dbgs() << "Comparison: " << Cmp << "\n");
728733
// Cannot handle comparison EQ, i.e. while (A == B).
729734
if (Cmp == Comparison::EQ)
730735
return nullptr;
@@ -840,6 +845,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
840845
if (IVBump < 0) {
841846
std::swap(Start, End);
842847
IVBump = -IVBump;
848+
std::swap(CmpLess, CmpGreater);
843849
}
844850
// Cmp may now have a wrong direction, e.g. LEs may now be GEs.
845851
// Signedness, and "including equality" are preserved.
@@ -983,7 +989,45 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
983989
CountSR = 0;
984990
}
985991

986-
return new CountValue(CountValue::CV_Register, CountR, CountSR);
992+
const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
993+
Register MuxR = CountR;
994+
unsigned MuxSR = CountSR;
995+
// For the loop count to be valid unsigned number, CmpLess should imply
996+
// Dist >= 0. Similarly, CmpGreater should imply Dist < 0. We can skip the
997+
// check if the initial distance is zero and the comparison is LTu || LTEu.
998+
if (!(Start->isImm() && StartV == 0 && Comparison::isUnsigned(Cmp) &&
999+
CmpLess) &&
1000+
(CmpLess || CmpGreater)) {
1001+
// Generate:
1002+
// DistCheck = CMP_GT DistR, 0 --> CmpLess
1003+
// DistCheck = CMP_GT DistR, -1 --> CmpGreater
1004+
Register DistCheckR = MRI->createVirtualRegister(PredRC);
1005+
const MCInstrDesc &DistCheckD = TII->get(Hexagon::C2_cmpgti);
1006+
BuildMI(*PH, InsertPos, DL, DistCheckD, DistCheckR)
1007+
.addReg(DistR, 0, DistSR)
1008+
.addImm((CmpLess) ? 0 : -1);
1009+
1010+
// Generate:
1011+
// MUXR = MUX DistCheck, CountR, 1 --> CmpLess
1012+
// MUXR = MUX DistCheck, 1, CountR --> CmpGreater
1013+
MuxR = MRI->createVirtualRegister(IntRC);
1014+
if (CmpLess) {
1015+
const MCInstrDesc &MuxD = TII->get(Hexagon::C2_muxir);
1016+
BuildMI(*PH, InsertPos, DL, MuxD, MuxR)
1017+
.addReg(DistCheckR)
1018+
.addReg(CountR, 0, CountSR)
1019+
.addImm(1);
1020+
} else {
1021+
const MCInstrDesc &MuxD = TII->get(Hexagon::C2_muxri);
1022+
BuildMI(*PH, InsertPos, DL, MuxD, MuxR)
1023+
.addReg(DistCheckR)
1024+
.addImm(1)
1025+
.addReg(CountR, 0, CountSR);
1026+
}
1027+
MuxSR = 0;
1028+
}
1029+
1030+
return new CountValue(CountValue::CV_Register, MuxR, MuxSR);
9871031
}
9881032

9891033
/// Return true if the operation is invalid within hardware loop.

‎llvm/test/CodeGen/Hexagon/hwloop-dist-check.mir

Lines changed: 277 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,277 @@
1+
# RUN: llc --mtriple=hexagon -run-pass=hwloops %s -o - | FileCheck %s
2+
3+
# CHECK-LABEL: name: f
4+
# CHECK: [[R1:%[0-9]+]]:predregs = C2_cmpgti [[R0:%[0-9]+]], 0
5+
# CHECK: [[R3:%[0-9]+]]:intregs = C2_muxir [[R1:%[0-9]+]], [[R2:%[0-9]+]], 1
6+
# CHECK-LABEL: name: g
7+
# CHECK: [[R1:%[0-9]+]]:predregs = C2_cmpgti [[R0:%[0-9]+]], 0
8+
# CHECK: [[R3:%[0-9]+]]:intregs = C2_muxir [[R1:%[0-9]+]], [[R2:%[0-9]+]], 1
9+
--- |
10+
@a = dso_local global [255 x ptr] zeroinitializer, align 8
11+
12+
; Function Attrs: minsize nofree norecurse nosync nounwind optsize memory(write, argmem: none, inaccessiblemem: none)
13+
define dso_local void @f(i32 noundef %m) local_unnamed_addr #0 {
14+
entry:
15+
%cond = tail call i32 @llvm.smax.i32(i32 %m, i32 2)
16+
%0 = add nsw i32 %cond, -4
17+
%1 = shl i32 %cond, 3
18+
%cgep = getelementptr i8, ptr @a, i32 %1
19+
%cgep36 = bitcast ptr @a to ptr
20+
br label %do.body
21+
22+
do.body: ; preds = %do.body, %entry
23+
%lsr.iv1 = phi ptr [ %cgep4, %do.body ], [ %cgep, %entry ]
24+
%lsr.iv = phi i32 [ %lsr.iv.next, %do.body ], [ %0, %entry ]
25+
%sh.0 = phi i32 [ 256, %entry ], [ %shr, %do.body ]
26+
%shr = lshr i32 %sh.0, 1
27+
%cgep5 = getelementptr inbounds [255 x ptr], ptr %cgep36, i32 0, i32 %shr
28+
store ptr %lsr.iv1, ptr %cgep5, align 4, !tbaa !5
29+
%lsr.iv.next = add nsw i32 %lsr.iv, 4
30+
%cmp1 = icmp samesign ult i32 %lsr.iv.next, 1073741836
31+
%cgep4 = getelementptr i8, ptr %lsr.iv1, i32 32
32+
br i1 %cmp1, label %do.body, label %do.end, !llvm.loop !9
33+
34+
do.end: ; preds = %do.body
35+
ret void
36+
}
37+
38+
; Function Attrs: minsize nofree norecurse nosync nounwind optsize memory(write, argmem: none, inaccessiblemem: none)
39+
define dso_local void @g(i32 noundef %m) local_unnamed_addr #0 {
40+
entry:
41+
%0 = add i32 %m, -4
42+
%1 = shl i32 %m, 3
43+
%cgep = getelementptr i8, ptr @a, i32 %1
44+
%cgep36 = bitcast ptr @a to ptr
45+
br label %do.body
46+
47+
do.body: ; preds = %do.body, %entry
48+
%lsr.iv1 = phi ptr [ %cgep4, %do.body ], [ %cgep, %entry ]
49+
%lsr.iv = phi i32 [ %lsr.iv.next, %do.body ], [ %0, %entry ]
50+
%sh.0 = phi i32 [ 256, %entry ], [ %shr, %do.body ]
51+
%shr = lshr i32 %sh.0, 1
52+
%cgep5 = getelementptr inbounds [255 x ptr], ptr %cgep36, i32 0, i32 %shr
53+
store ptr %lsr.iv1, ptr %cgep5, align 4, !tbaa !5
54+
%lsr.iv.next = add i32 %lsr.iv, 4
55+
%cmp = icmp slt i32 %lsr.iv.next, 1073741836
56+
%cgep4 = getelementptr i8, ptr %lsr.iv1, i32 32
57+
br i1 %cmp, label %do.body, label %do.end, !llvm.loop !11
58+
59+
do.end: ; preds = %do.body
60+
ret void
61+
}
62+
63+
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
64+
declare i32 @llvm.smax.i32(i32, i32) #1
65+
66+
!llvm.module.flags = !{!0, !1, !2, !3}
67+
!0 = !{i32 1, !"wchar_size", i32 4}
68+
!1 = !{i32 8, !"PIC Level", i32 2}
69+
!2 = !{i32 7, !"PIE Level", i32 2}
70+
!3 = !{i32 7, !"frame-pointer", i32 2}
71+
!5 = !{!6, !6, i64 0}
72+
!6 = !{!"any pointer", !7, i64 0}
73+
!7 = !{!"omnipotent char", !8, i64 0}
74+
!8 = !{!"Simple C/C++ TBAA"}
75+
!9 = distinct !{!9, !10}
76+
!10 = !{!"llvm.loop.mustprogress"}
77+
!11 = distinct !{!11, !10}
78+
79+
...
80+
---
81+
name: f
82+
alignment: 4
83+
exposesReturnsTwice: false
84+
legalized: false
85+
regBankSelected: false
86+
selected: false
87+
failedISel: false
88+
tracksRegLiveness: true
89+
hasWinCFI: false
90+
noPhis: false
91+
isSSA: true
92+
noVRegs: false
93+
hasFakeUses: false
94+
callsEHReturn: false
95+
callsUnwindInit: false
96+
hasEHScopes: false
97+
hasEHFunclets: false
98+
isOutlined: false
99+
debugInstrRef: false
100+
failsVerification: false
101+
tracksDebugUserValues: false
102+
registers:
103+
- { id: 0, class: intregs, preferred-register: '', flags: [ ] }
104+
- { id: 1, class: intregs, preferred-register: '', flags: [ ] }
105+
- { id: 2, class: intregs, preferred-register: '', flags: [ ] }
106+
- { id: 3, class: intregs, preferred-register: '', flags: [ ] }
107+
- { id: 4, class: intregs, preferred-register: '', flags: [ ] }
108+
- { id: 5, class: intregs, preferred-register: '', flags: [ ] }
109+
- { id: 6, class: intregs, preferred-register: '', flags: [ ] }
110+
- { id: 7, class: intregs, preferred-register: '', flags: [ ] }
111+
- { id: 8, class: intregs, preferred-register: '', flags: [ ] }
112+
- { id: 9, class: intregs, preferred-register: '', flags: [ ] }
113+
- { id: 10, class: intregs, preferred-register: '', flags: [ ] }
114+
- { id: 11, class: intregs, preferred-register: '', flags: [ ] }
115+
- { id: 12, class: intregs, preferred-register: '', flags: [ ] }
116+
- { id: 13, class: predregs, preferred-register: '', flags: [ ] }
117+
- { id: 14, class: predregs, preferred-register: '', flags: [ ] }
118+
- { id: 15, class: intregs, preferred-register: '', flags: [ ] }
119+
liveins:
120+
- { reg: '$r0', virtual-reg: '%9' }
121+
frameInfo:
122+
isFrameAddressTaken: false
123+
isReturnAddressTaken: false
124+
hasStackMap: false
125+
hasPatchPoint: false
126+
stackSize: 0
127+
offsetAdjustment: 0
128+
maxAlignment: 1
129+
adjustsStack: false
130+
hasCalls: false
131+
stackProtector: ''
132+
functionContext: ''
133+
maxCallFrameSize: 4294967295
134+
cvBytesOfCalleeSavedRegisters: 0
135+
hasOpaqueSPAdjustment: false
136+
hasVAStart: false
137+
hasMustTailInVarArgFunc: false
138+
hasTailCall: false
139+
isCalleeSavedInfoValid: false
140+
localFrameSize: 0
141+
savePoint: ''
142+
restorePoint: ''
143+
fixedStack: []
144+
stack: []
145+
entry_values: []
146+
callSites: []
147+
debugValueSubstitutions: []
148+
constants: []
149+
machineFunctionInfo: {}
150+
body: |
151+
bb.0.entry:
152+
successors: %bb.1(0x80000000)
153+
liveins: $r0
154+
155+
%9:intregs = COPY $r0
156+
%11:intregs = A2_tfrsi 2
157+
%12:intregs = A2_max %9, %11
158+
%0:intregs = nsw A2_addi %12, -4
159+
%1:intregs = S4_addi_asl_ri @a, %12, 3
160+
%2:intregs = A2_tfrsi @a
161+
%10:intregs = A2_tfrsi 256
162+
163+
bb.1.do.body:
164+
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
165+
166+
%3:intregs = PHI %1, %bb.0, %8, %bb.1
167+
%4:intregs = PHI %0, %bb.0, %7, %bb.1
168+
%5:intregs = PHI %10, %bb.0, %15, %bb.1
169+
%15:intregs = S2_extractu %5, 8, 1
170+
S4_storeri_rr %2, %15, 2, %3 :: (store (s32) into %ir.cgep5, !tbaa !5)
171+
%7:intregs = nsw A2_addi %4, 4
172+
%13:predregs = C2_cmpgtui %7, 1073741835
173+
%8:intregs = A2_addi %3, 32
174+
J2_jumpf %13, %bb.1, implicit-def dead $pc
175+
J2_jump %bb.2, implicit-def dead $pc
176+
177+
bb.2.do.end:
178+
PS_jmpret $r31, implicit-def dead $pc
179+
180+
...
181+
---
182+
name: g
183+
alignment: 4
184+
exposesReturnsTwice: false
185+
legalized: false
186+
regBankSelected: false
187+
selected: false
188+
failedISel: false
189+
tracksRegLiveness: true
190+
hasWinCFI: false
191+
noPhis: false
192+
isSSA: true
193+
noVRegs: false
194+
hasFakeUses: false
195+
callsEHReturn: false
196+
callsUnwindInit: false
197+
hasEHScopes: false
198+
hasEHFunclets: false
199+
isOutlined: false
200+
debugInstrRef: false
201+
failsVerification: false
202+
tracksDebugUserValues: false
203+
registers:
204+
- { id: 0, class: intregs, preferred-register: '', flags: [ ] }
205+
- { id: 1, class: intregs, preferred-register: '', flags: [ ] }
206+
- { id: 2, class: intregs, preferred-register: '', flags: [ ] }
207+
- { id: 3, class: intregs, preferred-register: '', flags: [ ] }
208+
- { id: 4, class: intregs, preferred-register: '', flags: [ ] }
209+
- { id: 5, class: intregs, preferred-register: '', flags: [ ] }
210+
- { id: 6, class: intregs, preferred-register: '', flags: [ ] }
211+
- { id: 7, class: intregs, preferred-register: '', flags: [ ] }
212+
- { id: 8, class: intregs, preferred-register: '', flags: [ ] }
213+
- { id: 9, class: intregs, preferred-register: '', flags: [ ] }
214+
- { id: 10, class: intregs, preferred-register: '', flags: [ ] }
215+
- { id: 11, class: predregs, preferred-register: '', flags: [ ] }
216+
- { id: 12, class: predregs, preferred-register: '', flags: [ ] }
217+
- { id: 13, class: intregs, preferred-register: '', flags: [ ] }
218+
liveins:
219+
- { reg: '$r0', virtual-reg: '%9' }
220+
frameInfo:
221+
isFrameAddressTaken: false
222+
isReturnAddressTaken: false
223+
hasStackMap: false
224+
hasPatchPoint: false
225+
stackSize: 0
226+
offsetAdjustment: 0
227+
maxAlignment: 1
228+
adjustsStack: false
229+
hasCalls: false
230+
stackProtector: ''
231+
functionContext: ''
232+
maxCallFrameSize: 4294967295
233+
cvBytesOfCalleeSavedRegisters: 0
234+
hasOpaqueSPAdjustment: false
235+
hasVAStart: false
236+
hasMustTailInVarArgFunc: false
237+
hasTailCall: false
238+
isCalleeSavedInfoValid: false
239+
localFrameSize: 0
240+
savePoint: ''
241+
restorePoint: ''
242+
fixedStack: []
243+
stack: []
244+
entry_values: []
245+
callSites: []
246+
debugValueSubstitutions: []
247+
constants: []
248+
machineFunctionInfo: {}
249+
body: |
250+
bb.0.entry:
251+
successors: %bb.1(0x80000000)
252+
liveins: $r0
253+
254+
%9:intregs = COPY $r0
255+
%0:intregs = A2_addi %9, -4
256+
%1:intregs = S4_addi_asl_ri @a, %9, 3
257+
%2:intregs = A2_tfrsi @a
258+
%10:intregs = A2_tfrsi 256
259+
260+
bb.1.do.body:
261+
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
262+
263+
%3:intregs = PHI %1, %bb.0, %8, %bb.1
264+
%4:intregs = PHI %0, %bb.0, %7, %bb.1
265+
%5:intregs = PHI %10, %bb.0, %13, %bb.1
266+
%13:intregs = S2_extractu %5, 8, 1
267+
S4_storeri_rr %2, %13, 2, %3 :: (store (s32) into %ir.cgep5, !tbaa !5)
268+
%7:intregs = A2_addi %4, 4
269+
%11:predregs = C2_cmpgti %7, 1073741835
270+
%8:intregs = A2_addi %3, 32
271+
J2_jumpf %11, %bb.1, implicit-def dead $pc
272+
J2_jump %bb.2, implicit-def dead $pc
273+
274+
bb.2.do.end:
275+
PS_jmpret $r31, implicit-def dead $pc
276+
277+
...

‎llvm/test/CodeGen/Hexagon/swp-phi-start.ll

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,9 @@
55
; the same stage.
66

77
; CHECK-DAG: [[REG3:(r[0-9]+)]] = add([[REG1:(r[0-9]+)]],#-1)
8-
; CHECK-DAG: [[REG2:(r[0-9]+)]] = add([[REG1]],#-1)
9-
; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],[[REG3]])
8+
; CHECK-DAG: [[REG2:(r[0-9]+)]] = add([[REG4:(r[0-9]+)]],#-1)
9+
; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],[[REG2]])
10+
; CHECK-NOT: = [[REG3]]
1011
; CHECK-NOT: = [[REG2]]
1112
; CHECK: .LBB0_[[LOOP]]:
1213
; CHECK: }{{[ \t]*}}:endloop

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