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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--linux-gnu"
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- define void @outer ([4 x i32 ]* %ptr , i32 %i ) {
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+ define void @outer1 ([4 x i32 ]* %ptr , i32 %i ) {
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call void @inner1 ([4 x i32 ]* %ptr , i32 %i )
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+ ret void
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+ }
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+
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+ define void @outer2 ([4 x i32 ]* %ptr , i32 %i ) {
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call void @inner2 ([4 x i32 ]* %ptr , i32 %i )
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ret void
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}
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+
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+ define void @outer3 ([4 x i32 ]* %ptr , i32 %j ) {
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+ call void @inner3 ([4 x i32 ]* %ptr , i32 0 , i32 %j )
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+ ret void
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+ }
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+
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; The gep in inner1() is reg+reg, which is a legal addressing mode for AArch64.
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; Thus, both the gep and ret can be simplified.
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; CHECK: Analyzing call of inner1
@@ -19,7 +29,7 @@ define void @inner1([4 x i32]* %ptr, i32 %i) {
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ret void
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}
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- ; The gep in inner2() is reg+imm+reg, which is not a legal addressing mode for
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+ ; The gep in inner2() is reg+imm+reg, which is not a legal addressing mode for
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; AArch64. Thus, only the ret can be simplified and not the gep.
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; CHECK: Analyzing call of inner2
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; CHECK: NumInstructionsSimplified: 1
@@ -28,3 +38,14 @@ define void @inner2([4 x i32]* %ptr, i32 %i) {
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%G = getelementptr inbounds [4 x i32 ], [4 x i32 ]* %ptr , i32 1 , i32 %i
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ret void
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}
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+
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+ ; The gep in inner3() is reg+reg because %i is a known constant from the
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+ ; callsite. This case is a legal addressing mode for AArch64. Thus, both the
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+ ; gep and ret can be simplified.
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+ ; CHECK: Analyzing call of inner3
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+ ; CHECK: NumInstructionsSimplified: 2
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+ ; CHECK: NumInstructions: 2
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+ define void @inner3 ([4 x i32 ]* %ptr , i32 %i , i32 %j ) {
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+ %G = getelementptr inbounds [4 x i32 ], [4 x i32 ]* %ptr , i32 %i , i32 %j
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+ ret void
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+ }
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