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[SDAG] Fix CombineTo ordering in visitZERO_EXTEND and visitSIGN_EXTEND
Reorder CombineTo Calls to prevent references to stale/deleted SDNodes which caused undue assertions. Reviewers: dbabokin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D31625 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304460 91177308-0d34-0410-b5e6-96231b3b80d8
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+140
-89
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2 files changed

+140
-89
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‎lib/CodeGen/SelectionDAG/DAGCombiner.cpp

+8-15
Original file line numberDiff line numberDiff line change
@@ -7227,12 +7227,11 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
72277227
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, LN0->getChain(),
72287228
LN0->getBasePtr(), N0.getValueType(),
72297229
LN0->getMemOperand());
7230-
CombineTo(N, ExtLoad);
72317230
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
72327231
N0.getValueType(), ExtLoad);
7233-
CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
72347232
ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::SIGN_EXTEND);
7235-
return SDValue(N, 0); // Return N so it doesn't get rechecked!
7233+
CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
7234+
return CombineTo(N, ExtLoad); // Return N so it doesn't get rechecked!
72367235
}
72377236
}
72387237

@@ -7288,10 +7287,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
72887287
SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
72897288
SDLoc(N0.getOperand(0)),
72907289
N0.getOperand(0).getValueType(), ExtLoad);
7291-
CombineTo(N, And);
7292-
CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
72937290
ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::SIGN_EXTEND);
7294-
return SDValue(N, 0); // Return N so it doesn't get rechecked!
7291+
CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
7292+
return CombineTo(N, And); // Return N so it doesn't get rechecked!
72957293
}
72967294
}
72977295
}
@@ -7530,12 +7528,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
75307528

75317529
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
75327530
N0.getValueType(), ExtLoad);
7531+
ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), ISD::ZERO_EXTEND);
75337532
CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
7534-
7535-
ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
7536-
ISD::ZERO_EXTEND);
7537-
CombineTo(N, ExtLoad);
7538-
return SDValue(N, 0); // Return N so it doesn't get rechecked!
7533+
return CombineTo(N, ExtLoad); // Return N so it doesn't get rechecked!
75397534
}
75407535
}
75417536

@@ -7585,11 +7580,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
75857580
SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
75867581
SDLoc(N0.getOperand(0)),
75877582
N0.getOperand(0).getValueType(), ExtLoad);
7588-
CombineTo(N, And);
7583+
ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::ZERO_EXTEND);
75897584
CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
7590-
ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL,
7591-
ISD::ZERO_EXTEND);
7592-
return SDValue(N, 0); // Return N so it doesn't get rechecked!
7585+
return CombineTo(N, And); // Return N so it doesn't get rechecked!
75937586
}
75947587
}
75957588
}

‎test/CodeGen/X86/pr32284.ll

+132-74
Original file line numberDiff line numberDiff line change
@@ -1,81 +1,17 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=i686-unknown -mcpu=skx | FileCheck %s --check-prefix=X86
3-
; RUN: llc < %s -mtriple=i686-unknown -mcpu=skx -O0 | FileCheck %s --check-prefix=X86-O0
4-
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s --check-prefix=X64
5-
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx -O0 | FileCheck %s --check-prefix=X64-O0
1+
; RUN: llc -O0 -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefixes=CHECK,X64
2+
; RUN: llc -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefixes=CHECK,X64
3+
; RUN: llc -O0 -mtriple=i686-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefixes=CHECK,686
4+
; RUN: llc -mtriple=i686-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefixes=CHECK,686
5+
; REQUIRES: asserts
66

77
@c = external constant i8, align 1
88

99
define void @foo() {
10-
; X86-LABEL: foo:
11-
; X86: # BB#0: # %entry
12-
; X86-NEXT: subl $8, %esp
13-
; X86-NEXT: .Lcfi0:
14-
; X86-NEXT: .cfi_def_cfa_offset 12
15-
; X86-NEXT: movzbl c, %eax
16-
; X86-NEXT: xorl %ecx, %ecx
17-
; X86-NEXT: testl %eax, %eax
18-
; X86-NEXT: setne %cl
19-
; X86-NEXT: testb %al, %al
20-
; X86-NEXT: setne {{[0-9]+}}(%esp)
21-
; X86-NEXT: xorl %edx, %edx
22-
; X86-NEXT: cmpl %eax, %ecx
23-
; X86-NEXT: setle %dl
24-
; X86-NEXT: movl %edx, {{[0-9]+}}(%esp)
25-
; X86-NEXT: addl $8, %esp
26-
; X86-NEXT: retl
27-
;
28-
; X86-O0-LABEL: foo:
29-
; X86-O0: # BB#0: # %entry
30-
; X86-O0-NEXT: subl $12, %esp
31-
; X86-O0-NEXT: .Lcfi0:
32-
; X86-O0-NEXT: .cfi_def_cfa_offset 16
33-
; X86-O0-NEXT: movb c, %al
34-
; X86-O0-NEXT: testb %al, %al
35-
; X86-O0-NEXT: setne {{[0-9]+}}(%esp)
36-
; X86-O0-NEXT: movzbl c, %ecx
37-
; X86-O0-NEXT: testl %ecx, %ecx
38-
; X86-O0-NEXT: setne %al
39-
; X86-O0-NEXT: movzbl %al, %edx
40-
; X86-O0-NEXT: subl %ecx, %edx
41-
; X86-O0-NEXT: setle %al
42-
; X86-O0-NEXT: andb $1, %al
43-
; X86-O0-NEXT: movzbl %al, %ecx
44-
; X86-O0-NEXT: movl %ecx, {{[0-9]+}}(%esp)
45-
; X86-O0-NEXT: movl %edx, (%esp) # 4-byte Spill
46-
; X86-O0-NEXT: addl $12, %esp
47-
; X86-O0-NEXT: retl
48-
;
49-
; X64-LABEL: foo:
50-
; X64: # BB#0: # %entry
51-
; X64-NEXT: movzbl {{.*}}(%rip), %eax
52-
; X64-NEXT: testb %al, %al
53-
; X64-NEXT: setne -{{[0-9]+}}(%rsp)
54-
; X64-NEXT: xorl %ecx, %ecx
55-
; X64-NEXT: testl %eax, %eax
56-
; X64-NEXT: setne %cl
57-
; X64-NEXT: xorl %edx, %edx
58-
; X64-NEXT: cmpl %eax, %ecx
59-
; X64-NEXT: setle %dl
60-
; X64-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
61-
; X64-NEXT: retq
62-
;
63-
; X64-O0-LABEL: foo:
64-
; X64-O0: # BB#0: # %entry
65-
; X64-O0-NEXT: movb {{.*}}(%rip), %al
66-
; X64-O0-NEXT: testb %al, %al
67-
; X64-O0-NEXT: setne -{{[0-9]+}}(%rsp)
68-
; X64-O0-NEXT: movzbl {{.*}}(%rip), %ecx
69-
; X64-O0-NEXT: testl %ecx, %ecx
70-
; X64-O0-NEXT: setne %al
71-
; X64-O0-NEXT: movzbl %al, %edx
72-
; X64-O0-NEXT: subl %ecx, %edx
73-
; X64-O0-NEXT: setle %al
74-
; X64-O0-NEXT: andb $1, %al
75-
; X64-O0-NEXT: movzbl %al, %ecx
76-
; X64-O0-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
77-
; X64-O0-NEXT: movl %edx, -{{[0-9]+}}(%rsp) # 4-byte Spill
78-
; X64-O0-NEXT: retq
10+
; CHECK-LABEL: foo:
11+
; CHECK: # BB#0: # %entry
12+
; CHECK-DAG: setne
13+
; CHECK-DAG: setle
14+
; CHECK: ret
7915
entry:
8016
%a = alloca i8, align 1
8117
%b = alloca i32, align 4
@@ -100,3 +36,125 @@ entry:
10036
store i32 %conv8, i32* %b, align 4
10137
ret void
10238
}
39+
40+
@var_5 = external global i32, align 4
41+
@var_57 = external global i64, align 8
42+
@_ZN8struct_210member_2_0E = external global i64, align 8
43+
44+
define void @f1() {
45+
; CHECK-LABEL: f1:
46+
; CHECK: # BB#0: # %entry
47+
; CHECK: sete
48+
; X64: addq $7093, {{.*}}
49+
; 686: addl $7093, {{.*}}
50+
; CHECK: ret
51+
entry:
52+
%a = alloca i8, align 1
53+
%0 = load i32, i32* @var_5, align 4
54+
%conv = sext i32 %0 to i64
55+
%add = add nsw i64 %conv, 8381627093
56+
%tobool = icmp ne i64 %add, 0
57+
%frombool = zext i1 %tobool to i8
58+
store i8 %frombool, i8* %a, align 1
59+
%1 = load i32, i32* @var_5, align 4
60+
%neg = xor i32 %1, -1
61+
%tobool1 = icmp ne i32 %neg, 0
62+
%lnot = xor i1 %tobool1, true
63+
%conv2 = zext i1 %lnot to i64
64+
%2 = load i32, i32* @var_5, align 4
65+
%conv3 = sext i32 %2 to i64
66+
%add4 = add nsw i64 %conv3, 7093
67+
%cmp = icmp sgt i64 %conv2, %add4
68+
%conv5 = zext i1 %cmp to i64
69+
store i64 %conv5, i64* @var_57, align 8
70+
%3 = load i32, i32* @var_5, align 4
71+
%neg6 = xor i32 %3, -1
72+
%tobool7 = icmp ne i32 %neg6, 0
73+
%lnot8 = xor i1 %tobool7, true
74+
%conv9 = zext i1 %lnot8 to i64
75+
store i64 %conv9, i64* @_ZN8struct_210member_2_0E, align 8
76+
ret void
77+
}
78+
79+
80+
@var_7 = external global i8, align 1
81+
82+
define void @f2() {
83+
; CHECK-LABEL: f2:
84+
; CHECK: # BB#0: # %entry
85+
; X64: movzbl {{.*}}(%rip), %[[R:[a-z]*]]
86+
; 686: movzbl {{.*}}, %[[R:[a-z]*]]
87+
; CHECK: test{{[qlwb]}} %[[R]], %[[R]]
88+
; CHECK: sete {{.*}}
89+
; CHECK: ret
90+
entry:
91+
%a = alloca i16, align 2
92+
%0 = load i8, i8* @var_7, align 1
93+
%conv = zext i8 %0 to i32
94+
%1 = load i8, i8* @var_7, align 1
95+
%tobool = icmp ne i8 %1, 0
96+
%lnot = xor i1 %tobool, true
97+
%conv1 = zext i1 %lnot to i32
98+
%xor = xor i32 %conv, %conv1
99+
%conv2 = trunc i32 %xor to i16
100+
store i16 %conv2, i16* %a, align 2
101+
%2 = load i8, i8* @var_7, align 1
102+
%conv3 = zext i8 %2 to i16
103+
%tobool4 = icmp ne i16 %conv3, 0
104+
%lnot5 = xor i1 %tobool4, true
105+
%conv6 = zext i1 %lnot5 to i32
106+
%3 = load i8, i8* @var_7, align 1
107+
%conv7 = zext i8 %3 to i32
108+
%cmp = icmp eq i32 %conv6, %conv7
109+
%conv8 = zext i1 %cmp to i32
110+
%conv9 = trunc i32 %conv8 to i16
111+
store i16 %conv9, i16* undef, align 2
112+
ret void
113+
}
114+
115+
116+
@var_13 = external global i32, align 4
117+
@var_16 = external global i32, align 4
118+
@var_46 = external global i32, align 4
119+
120+
define void @f3() #0 {
121+
; CHECK-LABEL: f3:
122+
; X64-DAG: movl var_13(%rip), {{.*}}
123+
; X64-DAG: movl var_16(%rip), {{.*}}
124+
; X64-DAG: movl {{.*}},{{.*}}var_46{{.*}}
125+
; X64: retq
126+
; 686-DAG: movl var_13, {{.*}}
127+
; 686-DAG: movl var_16, {{.*}}
128+
; 686-DAG: movl {{.*}},{{.*}}var_46{{.*}}
129+
; 686: retl
130+
entry:
131+
%a = alloca i64, align 8
132+
%0 = load i32, i32* @var_13, align 4
133+
%neg = xor i32 %0, -1
134+
%conv = zext i32 %neg to i64
135+
%1 = load i32, i32* @var_13, align 4
136+
%tobool = icmp ne i32 %1, 0
137+
%lnot = xor i1 %tobool, true
138+
%conv1 = zext i1 %lnot to i64
139+
%2 = load i32, i32* @var_13, align 4
140+
%neg2 = xor i32 %2, -1
141+
%3 = load i32, i32* @var_16, align 4
142+
%xor = xor i32 %neg2, %3
143+
%conv3 = zext i32 %xor to i64
144+
%and = and i64 %conv1, %conv3
145+
%or = or i64 %conv, %and
146+
store i64 %or, i64* %a, align 8
147+
%4 = load i32, i32* @var_13, align 4
148+
%neg4 = xor i32 %4, -1
149+
%conv5 = zext i32 %neg4 to i64
150+
%5 = load i32, i32* @var_13, align 4
151+
%tobool6 = icmp ne i32 %5, 0
152+
%lnot7 = xor i1 %tobool6, true
153+
%conv8 = zext i1 %lnot7 to i64
154+
%and9 = and i64 %conv8, 0
155+
%or10 = or i64 %conv5, %and9
156+
%conv11 = trunc i64 %or10 to i32
157+
store i32 %conv11, i32* @var_46, align 4
158+
ret void
159+
}
160+

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