Skip to content

Commit 2d9ba31

Browse files
fhahnAlexisPerry
fhahn
authored and
AlexisPerry
committed
[LV] Add more masked store cost tests with different masks.
Add additional masked store tests which caused crashes with earlier versions of llvm#92555.
1 parent 5b1e1e5 commit 2d9ba31

File tree

1 file changed

+151
-0
lines changed

1 file changed

+151
-0
lines changed

‎llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll

Lines changed: 151 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -102,10 +102,161 @@ exit:
102102
ret i32 0
103103
}
104104

105+
define void @test_scalar_cost_single_store_loop_invariant_cond(ptr %dst, i1 %c) #0 {
106+
; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_invariant_cond(
107+
; CHECK-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR0]] {
108+
; CHECK-NEXT: entry:
109+
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
110+
; CHECK: vector.ph:
111+
; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[DST]], i64 96
112+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i1> poison, i1 [[C]], i64 0
113+
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i1> [[BROADCAST_SPLATINSERT]], <8 x i1> poison, <8 x i32> zeroinitializer
114+
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
115+
; CHECK: vector.body:
116+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
117+
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4
118+
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
119+
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP0]]
120+
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0
121+
; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP1]], i32 4, <8 x i1> [[BROADCAST_SPLAT]])
122+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
123+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24
124+
; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
125+
; CHECK: middle.block:
126+
; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]]
127+
; CHECK: scalar.ph:
128+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[DST]], [[ENTRY:%.*]] ]
129+
; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
130+
; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
131+
; CHECK: loop.header:
132+
; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
133+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH]] ]
134+
; CHECK-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[LOOP_LATCH]]
135+
; CHECK: if.then:
136+
; CHECK-NEXT: store i32 0, ptr [[PTR_IV]], align 4
137+
; CHECK-NEXT: br label [[LOOP_LATCH]]
138+
; CHECK: loop.latch:
139+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 4
140+
; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[DST]], i64 [[IV_NEXT]]
141+
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 116
142+
; CHECK-NEXT: br i1 [[CMP_NOT]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]
143+
; CHECK: exit:
144+
; CHECK-NEXT: ret void
145+
;
146+
entry:
147+
br label %loop.header
148+
149+
loop.header:
150+
%ptr.iv = phi ptr [ %dst, %entry ], [ %ptr.iv.next, %loop.latch ]
151+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
152+
br i1 %c, label %if.then, label %loop.latch
153+
154+
if.then:
155+
store i32 0, ptr %ptr.iv, align 4
156+
br label %loop.latch
157+
158+
loop.latch:
159+
%iv.next = add i64 %iv, 4
160+
%ptr.iv.next = getelementptr i8, ptr %dst, i64 %iv.next
161+
%cmp.not = icmp eq i64 %iv, 116
162+
br i1 %cmp.not, label %exit, label %loop.header
163+
164+
exit:
165+
ret void
166+
}
167+
168+
define void @test_scalar_cost_single_store_loop_varying_cond(ptr %dst, ptr noalias %src) #0 {
169+
; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_varying_cond(
170+
; CHECK-SAME: ptr [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
171+
; CHECK-NEXT: entry:
172+
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
173+
; CHECK: vector.ph:
174+
; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[DST]], i64 96
175+
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
176+
; CHECK: vector.body:
177+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
178+
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4
179+
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
180+
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16
181+
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP0]]
182+
; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP1]]
183+
; CHECK-NEXT: [[OFFSET_IDX3:%.*]] = mul i64 [[INDEX]], 4
184+
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX3]], 0
185+
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX3]], 16
186+
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP2]]
187+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP3]]
188+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 0
189+
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0
190+
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x i32>, ptr [[TMP6]], align 4
191+
; CHECK-NEXT: [[WIDE_VEC4:%.*]] = load <16 x i32>, ptr [[TMP7]], align 4
192+
; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
193+
; CHECK-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <16 x i32> [[WIDE_VEC4]], <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
194+
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq <4 x i32> [[STRIDED_VEC]], <i32 123, i32 123, i32 123, i32 123>
195+
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq <4 x i32> [[STRIDED_VEC5]], <i32 123, i32 123, i32 123, i32 123>
196+
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0
197+
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 4
198+
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> zeroinitializer, ptr [[TMP10]], i32 4, <4 x i1> [[TMP8]])
199+
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> zeroinitializer, ptr [[TMP11]], i32 4, <4 x i1> [[TMP9]])
200+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
201+
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24
202+
; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
203+
; CHECK: middle.block:
204+
; CHECK-NEXT: br label [[SCALAR_PH]]
205+
; CHECK: scalar.ph:
206+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[DST]], [[ENTRY:%.*]] ]
207+
; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
208+
; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
209+
; CHECK: loop.header:
210+
; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
211+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH]] ]
212+
; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]
213+
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4
214+
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 123
215+
; CHECK-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[LOOP_LATCH]]
216+
; CHECK: if.then:
217+
; CHECK-NEXT: store i32 0, ptr [[PTR_IV]], align 4
218+
; CHECK-NEXT: br label [[LOOP_LATCH]]
219+
; CHECK: loop.latch:
220+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 4
221+
; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[DST]], i64 [[IV_NEXT]]
222+
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 116
223+
; CHECK-NEXT: br i1 [[CMP_NOT]], label [[EXIT:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP7:![0-9]+]]
224+
; CHECK: exit:
225+
; CHECK-NEXT: ret void
226+
;
227+
entry:
228+
br label %loop.header
229+
230+
loop.header:
231+
%ptr.iv = phi ptr [ %dst, %entry ], [ %ptr.iv.next, %loop.latch ]
232+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
233+
%gep.src = getelementptr inbounds i32, ptr %src, i64 %iv
234+
%l = load i32, ptr %gep.src
235+
%c = icmp eq i32 %l, 123
236+
br i1 %c, label %if.then, label %loop.latch
237+
238+
if.then:
239+
store i32 0, ptr %ptr.iv, align 4
240+
br label %loop.latch
241+
242+
loop.latch:
243+
%iv.next = add i64 %iv, 4
244+
%ptr.iv.next = getelementptr i8, ptr %dst, i64 %iv.next
245+
%cmp.not = icmp eq i64 %iv, 116
246+
br i1 %cmp.not, label %exit, label %loop.header
247+
248+
exit:
249+
ret void
250+
}
251+
105252
attributes #0 = { "min-legal-vector-width"="0" "target-cpu"="skylake-avx512" }
106253
;.
107254
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
108255
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
109256
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
110257
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
258+
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
259+
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
260+
; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
261+
; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
111262
;.

0 commit comments

Comments
 (0)