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add MissingFeatures::isPPC_FP128Ty()
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clang/include/clang/CIR/MissingFeatures.h

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@@ -228,6 +228,7 @@ struct MissingFeatures {
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static bool xray() { return false; }
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static bool buildConstrainedFPCall() { return false; }
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static bool emitEmptyRecordCheck() { return false; }
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static bool isPPC_FP128Ty() { return false; }
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// Inline assembly
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static bool asmGoto() { return false; }

clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp

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@@ -1660,6 +1660,7 @@ RValue CIRGenFunction::buildBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
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case Builtin::BI__builtin_signbit:
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case Builtin::BI__builtin_signbitf:
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case Builtin::BI__builtin_signbitl: {
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assert(!::cir::MissingFeatures::isPPC_FP128Ty());
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mlir::Value val = buildScalarExpr(E->getArg(0));
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auto ret = builder.createSignBit(getLoc(E->getBeginLoc()), val);
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return RValue::get(ret->getResult(0));

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

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@@ -4228,6 +4228,7 @@ class CIRSignBitOpLowering
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mlir::LogicalResult
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matchAndRewrite(mlir::cir::SignBitOp op, OpAdaptor adaptor,
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mlir::ConversionPatternRewriter &rewriter) const override {
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assert(!::cir::MissingFeatures::isPPC_FP128Ty());
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int width = getPrimitiveSizeInBits(op.getInput().getType());
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auto intTy = mlir::IntegerType::get(rewriter.getContext(), width);
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auto bitcast = rewriter.create<mlir::LLVM::BitcastOp>(op->getLoc(), intTy,

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