Skip to content

Commit 00437fb

Browse files
arsenmarsenm
committed
AMDGPU: Add v_mfma_f32_16x16x32_bf16 for gfx950
1 parent cdd1e27 commit 00437fb

File tree

13 files changed

+329
-5
lines changed

13 files changed

+329
-5
lines changed

‎clang/include/clang/Basic/BuiltinsAMDGPU.def

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -438,6 +438,7 @@ TARGET_BUILTIN(__builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4, "V4fV8ZiV8ZiV4f
438438
TARGET_BUILTIN(__builtin_amdgcn_mfma_scale_f32_32x32x64_f8f6f4, "V16fV8ZiV8ZiV16fIiIiIiiIii", "nc", "gfx950-insts")
439439

440440
TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x32_f16, "V4fV8hV8hV4fIiIiIi", "nc", "gfx950-insts")
441+
TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x32_bf16, "V4fV8yV8yV4fIiIiIi", "nc", "gfx950-insts")
441442
TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_f16, "V16fV8hV8hV16fIiIiIi", "nc", "gfx950-insts")
442443
TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_bf16, "V16fV8yV8yV16fIiIiIi", "nc", "gfx950-insts")
443444
TARGET_BUILTIN(__builtin_amdgcn_mfma_i32_16x16x64_i8, "V4iV4iV4iV4iIiIiIi", "nc", "gfx950-insts")

‎clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -460,4 +460,11 @@ v16i test_mfma_i32_32x32x32_i8(v4i a, v4i b, v16i c) {
460460
return __builtin_amdgcn_mfma_i32_32x32x32_i8(a, b, c, 1, 2, 3);
461461
}
462462

463+
// CHECK-GFX950-LABEL: @test_mfma_f32_16x16x32_bf16(
464+
// CHECK-GFX950: tail call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.bf16(<8 x bfloat> %a, <8 x bfloat> %b, <4 x float> %c, i32 1, i32 2, i32 3)
465+
v4f test_mfma_f32_16x16x32_bf16(v8bf16 a, v8bf16 b, v4f c)
466+
{
467+
return __builtin_amdgcn_mfma_f32_16x16x32_bf16(a, b, c, 1, 2, 3);
468+
}
469+
463470
#endif

‎clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,3 +55,10 @@ void test_mfma_i32_32x32x32_i8(__global int16* out, int4 a, int4 b, int16 c, int
5555
*out = __builtin_amdgcn_mfma_i32_32x32x32_i8(a, b, c, 0, X, 0); // expected-error{{argument to '__builtin_amdgcn_mfma_i32_32x32x32_i8' must be a constant integer}}
5656
*out = __builtin_amdgcn_mfma_i32_32x32x32_i8(a, b, c, 0, 0, X); // expected-error{{argument to '__builtin_amdgcn_mfma_i32_32x32x32_i8' must be a constant integer}}
5757
}
58+
59+
void test_mfma_f32_16x16x32_bf16(__global float4* out, bfloat8 a, bfloat8 b, float4 c, int X) {
60+
61+
*out = __builtin_amdgcn_mfma_f32_16x16x32_bf16(a, b, c, X, 0, 0); // expected-error{{argument to '__builtin_amdgcn_mfma_f32_16x16x32_bf16' must be a constant integer}}
62+
*out = __builtin_amdgcn_mfma_f32_16x16x32_bf16(a, b, c, 0, X, 0); // expected-error{{argument to '__builtin_amdgcn_mfma_f32_16x16x32_bf16' must be a constant integer}}
63+
*out = __builtin_amdgcn_mfma_f32_16x16x32_bf16(a, b, c, 0, 0, X); // expected-error{{argument to '__builtin_amdgcn_mfma_f32_16x16x32_bf16' must be a constant integer}}
64+
}

‎clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ void test(__global float4* out0, half8 a0, half8 b0, float4 c0,
3333
*out2 = __builtin_amdgcn_mfma_f32_32x32x16_bf16(a2, b2, c2, 0, 0, 0); // expected-error{{'__builtin_amdgcn_mfma_f32_32x32x16_bf16' needs target feature gfx950-insts}}
3434
*out3 = __builtin_amdgcn_mfma_i32_16x16x64_i8(a3, b3, c3, 0, 0, 0); // expected-error{{'__builtin_amdgcn_mfma_i32_16x16x64_i8' needs target feature gfx950-insts}}
3535
*out4 = __builtin_amdgcn_mfma_i32_32x32x32_i8(a4, b4, c4, 0, 0, 0); // expected-error{{'__builtin_amdgcn_mfma_i32_32x32x32_i8' needs target feature gfx950-insts}}
36+
*out5 = __builtin_amdgcn_mfma_f32_16x16x32_bf16(a5, b5, c5, 0, 0, 0); // expected-error{{'__builtin_amdgcn_mfma_f32_16x16x32_bf16' needs target feature gfx950-insts}}
3637
*out14 = __builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4(a14, b14, c14, 0, 0, 0, d14, 0, e14); // expected-error{{'__builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4' needs target feature gfx950-insts}}
3738
*out15 = __builtin_amdgcn_mfma_scale_f32_32x32x64_f8f6f4(a15, b15, c15, 0, 0, 0, d15, 0, e15); // expected-error{{'__builtin_amdgcn_mfma_scale_f32_32x32x64_f8f6f4' needs target feature gfx950-insts}}
3839
}

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3148,7 +3148,7 @@ def int_amdgcn_mfma_f32_16x16x32_f16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v
31483148
def int_amdgcn_mfma_f32_32x32x16_f16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v8f16_ty>;
31493149
def int_amdgcn_mfma_i32_16x16x64_i8 : AMDGPUMfmaIntrinsic<llvm_v4i32_ty, llvm_v4i32_ty>;
31503150
def int_amdgcn_mfma_i32_32x32x32_i8 : AMDGPUMfmaIntrinsic<llvm_v16i32_ty, llvm_v4i32_ty>;
3151-
3151+
def int_amdgcn_mfma_f32_16x16x32_bf16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v8bf16_ty>;
31523152
def int_amdgcn_mfma_f32_32x32x16_bf16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v8bf16_ty>;
31533153
def int_amdgcn_mfma_scale_f32_16x16x128_f8f6f4 : AMDGPUMfmaScaleIntrinsic<llvm_v4f32_ty>;
31543154
def int_amdgcn_mfma_scale_f32_32x32x64_f8f6f4 : AMDGPUMfmaScaleIntrinsic<llvm_v16f32_ty>;

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4751,7 +4751,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
47514751
case Intrinsic::amdgcn_mfma_f32_16x16x32_f16:
47524752
case Intrinsic::amdgcn_mfma_f32_32x32x16_f16:
47534753
case Intrinsic::amdgcn_mfma_i32_16x16x64_i8:
4754-
case Intrinsic::amdgcn_mfma_i32_32x32x32_i8: {
4754+
case Intrinsic::amdgcn_mfma_i32_32x32x32_i8:
4755+
case Intrinsic::amdgcn_mfma_f32_16x16x32_bf16: {
47554756
// Default for MAI intrinsics.
47564757
// srcC can also be an immediate which can be folded later.
47574758
// FIXME: Should we eventually add an alternative mapping with AGPR src

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2880,6 +2880,7 @@ def VOP_V16F32_V2I32_V4I32_I32 : VOPProfile <[v16f32, v2i32, v4i32, i32]>;
28802880
def VOP_V4F32_V8F16_V8F16_V4F32 : VOPProfile <[v4f32, v8f16, v8f16, v4f32]>;
28812881
def VOP_V16F32_V8F16_V8F16_V16F32 : VOPProfile <[v16f32, v8f16, v8f16, v16f32]>;
28822882
def VOP_V16F32_V8BF16_V8BF16_V16F32 : VOPProfile <[v16f32, v8bf16, v8bf16, v16f32]>;
2883+
def VOP_V4F32_V8BF16_V8BF16_V4F32 : VOPProfile <[v4f32, v8bf16, v8bf16, v4f32]>;
28832884
def VOP_V4F32_V8I32_V8I32_V4F32 : VOPProfile <[v4f32, v8i32, v8i32, v4f32]>;
28842885

28852886
def VOP_V4F32_V8I32_V6I32_V4F32 : VOPProfile <[v4f32, v8i32, v6i32, v4f32]>;

‎llvm/lib/Target/AMDGPU/VOP3PInstructions.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -645,6 +645,9 @@ def VOPProfileMAI_F32_V8F16_X16_VCD : VOPProfileMAI<VOP_V16F32_V8F16_V8F16_V16F3
645645
def VOPProfileMAI_F32_V8BF16_X16 : VOPProfileMAI<VOP_V16F32_V8BF16_V8BF16_V16F32, AISrc_512_f32, ADst_512, AVSrc_128>;
646646
def VOPProfileMAI_F32_V8BF16_X16_VCD : VOPProfileMAI<VOP_V16F32_V8BF16_V8BF16_V16F32, VISrc_512_f32, VDst_512, AVSrc_128>;
647647

648+
def VOPProfileMAI_F32_V8BF16_X4 : VOPProfileMAI<VOP_V4F32_V8BF16_V8BF16_V4F32, AISrc_128_f32, ADst_128, AVSrc_128>;
649+
def VOPProfileMAI_F32_V8BF16_X4_VCD : VOPProfileMAI<VOP_V4F32_V8BF16_V8BF16_V4F32, VISrc_128_f32, VDst_128, AVSrc_128>;
650+
648651

649652
let HasAbid = false in {
650653
// For f32_16x16x128_f8f6f4 - f8 x f8 case
@@ -952,6 +955,7 @@ defm V_MFMA_F32_32X32X4BF16 : MAIInst<"v_mfma_f32_32x32x4bf16", "F32_V2I16_X16",
952955
let SubtargetPredicate = HasGFX950Insts, is_gfx940_xdl = 1 in {
953956
defm V_MFMA_F32_16X16X32_F16 : MAIInst<"v_mfma_f32_16x16x32f16", "F32_V8F16_X32", int_amdgcn_mfma_f32_16x16x32_f16>;
954957
defm V_MFMA_F32_32X32X16_F16 : MAIInst<"v_mfma_f32_32x32x16f16", "F32_V8F16_X16", int_amdgcn_mfma_f32_32x32x16_f16>;
958+
defm V_MFMA_F32_16X16X32_BF16 : MAIInst<"v_mfma_f32_16x16x32bf16", "F32_V8BF16_X4", int_amdgcn_mfma_f32_16x16x32_bf16>;
955959
defm V_MFMA_I32_16X16X64_I8 : MAIInst<"v_mfma_i32_16x16x64i8", "I32_V4I32_X128", int_amdgcn_mfma_i32_16x16x64_i8>;
956960
defm V_MFMA_F32_32X32X16_BF16 : MAIInst<"v_mfma_f32_32x32x16bf16", "F32_V8BF16_X16", int_amdgcn_mfma_f32_32x32x16_bf16>;
957961
defm V_MFMA_I32_32X32X32_I8 : MAIInst<"v_mfma_i32_32x32x32i8", "I32_V4I32_X16", int_amdgcn_mfma_i32_32x32x32_i8>;
@@ -2078,6 +2082,7 @@ defm V_MFMA_F64_4X4X4F64 : VOP3P_Real_MFMA_gfx90a <0x6f>;
20782082

20792083
defm V_MFMA_F32_16X16X32_F16 : VOP3P_Real_MFMA_gfx950 <0x54, "v_mfma_f32_16x16x32_f16">;
20802084
defm V_MFMA_F32_32X32X16_F16 : VOP3P_Real_MFMA_gfx950 <0x55, "v_mfma_f32_32x32x16_f16">;
2085+
defm V_MFMA_F32_16X16X32_BF16 : VOP3P_Real_MFMA_gfx950 <0x35, "v_mfma_f32_16x16x32_bf16">;
20812086
defm V_MFMA_I32_16X16X64_I8 : VOP3P_Real_MFMA_gfx950 <0x36, "v_mfma_i32_16x16x64_i8">;
20822087
defm V_MFMA_F32_32X32X16_BF16 : VOP3P_Real_MFMA_gfx950 <0x37, "v_mfma_f32_32x32x16_bf16">;
20832088
defm V_MFMA_I32_32X32X32_I8 : VOP3P_Real_MFMA_gfx950 <0x38, "v_mfma_i32_32x32x32_i8">;

‎llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -323,6 +323,15 @@ define amdgpu_kernel void @mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32> %arg1
323323
ret void
324324
}
325325

326+
declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.bf16(<8 x bfloat>, <8 x bfloat>, <4 x float>, i32 immarg, i32 immarg, i32 immarg)
327+
328+
; CHECK: DIVERGENT: %result = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2, i32 immarg 0, i32 immarg 0, i32 immarg 0)
329+
define amdgpu_kernel void @mfma_f32_16x16x32_bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2, ptr addrspace(1) %out) {
330+
%result = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2, i32 immarg 0, i32 immarg 0, i32 immarg 0)
331+
store <4 x float> %result, ptr addrspace(1) %out
332+
ret void
333+
}
334+
326335
declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #1
327336
declare i32 @llvm.amdgcn.permlane16.i32(i32, i32, i32, i32, i1, i1) #1
328337
declare i32 @llvm.amdgcn.permlanex16.i32(i32, i32, i32, i32, i1, i1) #1

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll

Lines changed: 198 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1315,5 +1315,203 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd_mac_flags(<4 x i32>
13151315
ret void
13161316
}
13171317

1318+
; --------------------------------------------------------------------
1319+
; llvm.amdgcn.mfma.f32.16x16x32.bf16
1320+
; --------------------------------------------------------------------
1321+
1322+
declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.bf16(<8 x bfloat>, <8 x bfloat>, <4 x float>, i32 immarg, i32 immarg, i32 immarg)
1323+
1324+
define <4 x float> @test_mfma_f32_16x16x32_bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2) {
1325+
; SDAG-LABEL: test_mfma_f32_16x16x32_bf16:
1326+
; SDAG: ; %bb.0:
1327+
; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1328+
; SDAG-NEXT: v_accvgpr_write_b32 a0, v8
1329+
; SDAG-NEXT: v_accvgpr_write_b32 a1, v9
1330+
; SDAG-NEXT: v_accvgpr_write_b32 a2, v10
1331+
; SDAG-NEXT: v_accvgpr_write_b32 a3, v11
1332+
; SDAG-NEXT: s_nop 1
1333+
; SDAG-NEXT: v_mfma_f32_16x16x32_bf16 a[0:3], v[0:3], v[4:7], a[0:3]
1334+
; SDAG-NEXT: s_nop 6
1335+
; SDAG-NEXT: v_accvgpr_read_b32 v0, a0
1336+
; SDAG-NEXT: v_accvgpr_read_b32 v1, a1
1337+
; SDAG-NEXT: v_accvgpr_read_b32 v2, a2
1338+
; SDAG-NEXT: v_accvgpr_read_b32 v3, a3
1339+
; SDAG-NEXT: s_setpc_b64 s[30:31]
1340+
;
1341+
; GISEL-LABEL: test_mfma_f32_16x16x32_bf16:
1342+
; GISEL: ; %bb.0:
1343+
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1344+
; GISEL-NEXT: v_lshrrev_b32_e32 v12, 16, v0
1345+
; GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v1
1346+
; GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v2
1347+
; GISEL-NEXT: v_lshrrev_b32_e32 v15, 16, v3
1348+
; GISEL-NEXT: v_mov_b32_sdwa v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1349+
; GISEL-NEXT: v_mov_b32_sdwa v1, v13 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1350+
; GISEL-NEXT: v_mov_b32_sdwa v2, v14 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1351+
; GISEL-NEXT: v_mov_b32_sdwa v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1352+
; GISEL-NEXT: v_lshrrev_b32_e32 v12, 16, v4
1353+
; GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v5
1354+
; GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v6
1355+
; GISEL-NEXT: v_lshrrev_b32_e32 v15, 16, v7
1356+
; GISEL-NEXT: v_accvgpr_write_b32 a0, v8
1357+
; GISEL-NEXT: v_mov_b32_sdwa v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1358+
; GISEL-NEXT: v_mov_b32_sdwa v5, v13 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1359+
; GISEL-NEXT: v_mov_b32_sdwa v6, v14 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1360+
; GISEL-NEXT: v_mov_b32_sdwa v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1361+
; GISEL-NEXT: v_accvgpr_write_b32 a1, v9
1362+
; GISEL-NEXT: v_accvgpr_write_b32 a2, v10
1363+
; GISEL-NEXT: v_accvgpr_write_b32 a3, v11
1364+
; GISEL-NEXT: s_nop 1
1365+
; GISEL-NEXT: v_mfma_f32_16x16x32_bf16 a[0:3], v[0:3], v[4:7], a[0:3]
1366+
; GISEL-NEXT: s_nop 6
1367+
; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
1368+
; GISEL-NEXT: v_accvgpr_read_b32 v1, a1
1369+
; GISEL-NEXT: v_accvgpr_read_b32 v2, a2
1370+
; GISEL-NEXT: v_accvgpr_read_b32 v3, a3
1371+
; GISEL-NEXT: s_setpc_b64 s[30:31]
1372+
%result = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2, i32 0, i32 0, i32 0)
1373+
ret <4 x float> %result
1374+
}
1375+
1376+
define <4 x float> @test_mfma_f32_16x16x32_bf16__flags(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2) {
1377+
; SDAG-LABEL: test_mfma_f32_16x16x32_bf16__flags:
1378+
; SDAG: ; %bb.0:
1379+
; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1380+
; SDAG-NEXT: v_accvgpr_write_b32 a0, v8
1381+
; SDAG-NEXT: v_accvgpr_write_b32 a1, v9
1382+
; SDAG-NEXT: v_accvgpr_write_b32 a2, v10
1383+
; SDAG-NEXT: v_accvgpr_write_b32 a3, v11
1384+
; SDAG-NEXT: s_nop 1
1385+
; SDAG-NEXT: v_mfma_f32_16x16x32_bf16 a[0:3], v[0:3], v[4:7], a[0:3] cbsz:1 abid:1 blgp:1
1386+
; SDAG-NEXT: s_nop 6
1387+
; SDAG-NEXT: v_accvgpr_read_b32 v0, a0
1388+
; SDAG-NEXT: v_accvgpr_read_b32 v1, a1
1389+
; SDAG-NEXT: v_accvgpr_read_b32 v2, a2
1390+
; SDAG-NEXT: v_accvgpr_read_b32 v3, a3
1391+
; SDAG-NEXT: s_setpc_b64 s[30:31]
1392+
;
1393+
; GISEL-LABEL: test_mfma_f32_16x16x32_bf16__flags:
1394+
; GISEL: ; %bb.0:
1395+
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1396+
; GISEL-NEXT: v_lshrrev_b32_e32 v12, 16, v0
1397+
; GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v1
1398+
; GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v2
1399+
; GISEL-NEXT: v_lshrrev_b32_e32 v15, 16, v3
1400+
; GISEL-NEXT: v_mov_b32_sdwa v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1401+
; GISEL-NEXT: v_mov_b32_sdwa v1, v13 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1402+
; GISEL-NEXT: v_mov_b32_sdwa v2, v14 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1403+
; GISEL-NEXT: v_mov_b32_sdwa v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1404+
; GISEL-NEXT: v_lshrrev_b32_e32 v12, 16, v4
1405+
; GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v5
1406+
; GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v6
1407+
; GISEL-NEXT: v_lshrrev_b32_e32 v15, 16, v7
1408+
; GISEL-NEXT: v_accvgpr_write_b32 a0, v8
1409+
; GISEL-NEXT: v_mov_b32_sdwa v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1410+
; GISEL-NEXT: v_mov_b32_sdwa v5, v13 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1411+
; GISEL-NEXT: v_mov_b32_sdwa v6, v14 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1412+
; GISEL-NEXT: v_mov_b32_sdwa v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
1413+
; GISEL-NEXT: v_accvgpr_write_b32 a1, v9
1414+
; GISEL-NEXT: v_accvgpr_write_b32 a2, v10
1415+
; GISEL-NEXT: v_accvgpr_write_b32 a3, v11
1416+
; GISEL-NEXT: s_nop 1
1417+
; GISEL-NEXT: v_mfma_f32_16x16x32_bf16 a[0:3], v[0:3], v[4:7], a[0:3] cbsz:1 abid:1 blgp:1
1418+
; GISEL-NEXT: s_nop 6
1419+
; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
1420+
; GISEL-NEXT: v_accvgpr_read_b32 v1, a1
1421+
; GISEL-NEXT: v_accvgpr_read_b32 v2, a2
1422+
; GISEL-NEXT: v_accvgpr_read_b32 v3, a3
1423+
; GISEL-NEXT: s_setpc_b64 s[30:31]
1424+
%result = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2, i32 1, i32 1, i32 1)
1425+
ret <4 x float> %result
1426+
}
1427+
1428+
define amdgpu_kernel void @test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd(ptr addrspace(1) %out, <8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2) #0 {
1429+
; SDAG-LABEL: test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd:
1430+
; SDAG: ; %bb.0:
1431+
; SDAG-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
1432+
; SDAG-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
1433+
; SDAG-NEXT: v_mov_b32_e32 v12, 0
1434+
; SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1435+
; SDAG-NEXT: s_waitcnt lgkmcnt(0)
1436+
; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
1437+
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
1438+
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
1439+
; SDAG-NEXT: v_mov_b64_e32 v[8:9], s[12:13]
1440+
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
1441+
; SDAG-NEXT: v_mov_b64_e32 v[10:11], s[14:15]
1442+
; SDAG-NEXT: s_nop 1
1443+
; SDAG-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[0:3], v[4:7], v[8:11]
1444+
; SDAG-NEXT: s_nop 6
1445+
; SDAG-NEXT: global_store_dwordx4 v12, v[0:3], s[0:1]
1446+
; SDAG-NEXT: s_endpgm
1447+
;
1448+
; GISEL-LABEL: test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd:
1449+
; GISEL: ; %bb.0:
1450+
; GISEL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
1451+
; GISEL-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
1452+
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
1453+
; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
1454+
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
1455+
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
1456+
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[12:13]
1457+
; GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1458+
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
1459+
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[14:15]
1460+
; GISEL-NEXT: s_nop 1
1461+
; GISEL-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[0:3], v[4:7], v[8:11]
1462+
; GISEL-NEXT: v_mov_b32_e32 v4, 0
1463+
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
1464+
; GISEL-NEXT: s_nop 4
1465+
; GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
1466+
; GISEL-NEXT: s_endpgm
1467+
%result = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2, i32 0, i32 0, i32 0)
1468+
store <4 x float> %result, ptr addrspace(1) %out
1469+
ret void
1470+
}
1471+
1472+
define amdgpu_kernel void @test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd__flags(ptr addrspace(1) %out, <8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2) #0 {
1473+
; SDAG-LABEL: test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd__flags:
1474+
; SDAG: ; %bb.0:
1475+
; SDAG-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
1476+
; SDAG-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
1477+
; SDAG-NEXT: v_mov_b32_e32 v12, 0
1478+
; SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1479+
; SDAG-NEXT: s_waitcnt lgkmcnt(0)
1480+
; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
1481+
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
1482+
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
1483+
; SDAG-NEXT: v_mov_b64_e32 v[8:9], s[12:13]
1484+
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
1485+
; SDAG-NEXT: v_mov_b64_e32 v[10:11], s[14:15]
1486+
; SDAG-NEXT: s_nop 1
1487+
; SDAG-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[0:3], v[4:7], v[8:11] cbsz:3 abid:2 blgp:1
1488+
; SDAG-NEXT: s_nop 6
1489+
; SDAG-NEXT: global_store_dwordx4 v12, v[0:3], s[0:1]
1490+
; SDAG-NEXT: s_endpgm
1491+
;
1492+
; GISEL-LABEL: test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd__flags:
1493+
; GISEL: ; %bb.0:
1494+
; GISEL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
1495+
; GISEL-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
1496+
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
1497+
; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
1498+
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
1499+
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
1500+
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[12:13]
1501+
; GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1502+
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
1503+
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[14:15]
1504+
; GISEL-NEXT: s_nop 1
1505+
; GISEL-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[0:3], v[4:7], v[8:11] cbsz:3 abid:2 blgp:1
1506+
; GISEL-NEXT: v_mov_b32_e32 v4, 0
1507+
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
1508+
; GISEL-NEXT: s_nop 4
1509+
; GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
1510+
; GISEL-NEXT: s_endpgm
1511+
%result = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <4 x float> %arg2, i32 3, i32 2, i32 1)
1512+
store <4 x float> %result, ptr addrspace(1) %out
1513+
ret void
1514+
}
1515+
13181516
attributes #0 = { "amdgpu-flat-work-group-size"="512,512" }
13191517
attributes #1 = { "amdgpu-flat-work-group-size"="1,64" }

0 commit comments

Comments
 (0)