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AMDGPU: Replace some test i32 undef uses with poison
1 parent 024df9c commit 0045ccb

25 files changed

+57
-57
lines changed

‎llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -581,7 +581,7 @@ done:
581581

582582
; OPT-LABEL: @test_sink_local_small_offset_cmpxchg_i32(
583583
; OPT: %sunkaddr = getelementptr i8, ptr addrspace(3) %in, i32 28
584-
; OPT: %tmp1.struct = cmpxchg ptr addrspace(3) %sunkaddr, i32 undef, i32 2 seq_cst monotonic
584+
; OPT: %tmp1.struct = cmpxchg ptr addrspace(3) %sunkaddr, i32 poison, i32 2 seq_cst monotonic
585585
define amdgpu_kernel void @test_sink_local_small_offset_cmpxchg_i32(ptr addrspace(3) %out, ptr addrspace(3) %in) {
586586
entry:
587587
%out.gep = getelementptr i32, ptr addrspace(3) %out, i32 999999
@@ -591,7 +591,7 @@ entry:
591591
br i1 %tmp0, label %endif, label %if
592592

593593
if:
594-
%tmp1.struct = cmpxchg ptr addrspace(3) %in.gep, i32 undef, i32 2 seq_cst monotonic
594+
%tmp1.struct = cmpxchg ptr addrspace(3) %in.gep, i32 poison, i32 2 seq_cst monotonic
595595
%tmp1 = extractvalue { i32, i1 } %tmp1.struct, 0
596596
br label %endif
597597

‎llvm/test/CodeGen/AMDGPU/commute-shifts.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ define amdgpu_ps float @main(float %arg0, float %arg1) #0 {
3030
; VI-NEXT: ; return to shader part epilog
3131
bb:
3232
%tmp = fptosi float %arg0 to i32
33-
%tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> poison, i32 0, i32 0)
33+
%tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 poison, <8 x i32> poison, i32 0, i32 0)
3434
%tmp2.f = extractelement <4 x float> %tmp1, i32 0
3535
%tmp2 = bitcast float %tmp2.f to i32
3636
%tmp3 = and i32 %tmp, 7

‎llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -306,7 +306,7 @@ define amdgpu_vs float @load_addr_no_fold(ptr addrspace(6) inreg noalias %p0) #0
306306
define amdgpu_vs float @vgpr_arg_src(ptr addrspace(6) %arg) {
307307
main_body:
308308
%tmp9 = load ptr addrspace(8), ptr addrspace(6) %arg
309-
%tmp10 = call nsz float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp9, i32 undef, i32 0, i32 0, i32 0) #1
309+
%tmp10 = call nsz float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp9, i32 poison, i32 0, i32 0, i32 0) #1
310310
ret float %tmp10
311311
}
312312

‎llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
204204
%40 = fmul reassoc nnan nsz arcp contract afn float %39, 0x3F847AE140000000
205205
%41 = fadd reassoc nnan nsz arcp contract afn float %40, 0x3F947AE140000000
206206
%.i2415 = fmul reassoc nnan nsz arcp contract afn float %.i2407, %41
207-
%42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> poison, i32 0, i32 0)
207+
%42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 poison, i32 poison, i32 0, <8 x i32> poison, i32 0, i32 0)
208208
%.i2521 = extractelement <3 x float> %42, i32 2
209209
%43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
210210
%44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)

‎llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,11 +25,11 @@ define amdgpu_hs void @main(ptr addrspace(6) inreg %arg) {
2525
; GCN-NEXT: BUFFER_STORE_DWORDX3_OFFEN_exact killed [[COPY4]], [[COPY5]], [[DEF3]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s96) into `ptr addrspace(8) poison`, align 1, addrspace 8)
2626
; GCN-NEXT: S_ENDPGM 0
2727
main_body:
28-
%tmp25 = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) poison, i32 undef, i32 0, i32 0)
28+
%tmp25 = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) poison, i32 poison, i32 0, i32 0)
2929
%tmp27 = bitcast <4 x float> %tmp25 to <16 x i8>
3030
%tmp28 = shufflevector <16 x i8> %tmp27, <16 x i8> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
3131
%tmp29 = bitcast <12 x i8> %tmp28 to <3 x i32>
32-
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %tmp29, ptr addrspace(8) poison, i32 undef, i32 0, i32 0) #3
32+
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %tmp29, ptr addrspace(8) poison, i32 poison, i32 0, i32 0) #3
3333
ret void
3434
}
3535

‎llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
; GCN: IMAGE_LOAD_V4_V2
1212
define amdgpu_cs void @_amdgpu_cs_main(i32 %dummy) local_unnamed_addr #0 {
1313
.entry:
14-
%unused.result = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> poison, i32 0, i32 0) #3
14+
%unused.result = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 poison, i32 poison, <8 x i32> poison, i32 0, i32 0) #3
1515
call void asm sideeffect ";", "" () #0
1616
ret void
1717
}

‎llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ define amdgpu_kernel void @indirect_call_known_no_special_inputs() {
7575
bb:
7676
%cond = load i1, ptr addrspace(4) null
7777
%tmp = select i1 %cond, ptr @wobble, ptr @snork
78-
call void %tmp(ptr poison, i32 undef, ptr poison)
78+
call void %tmp(ptr poison, i32 poison, ptr poison)
7979
ret void
8080
}
8181

‎llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -185,7 +185,7 @@ sw.bb10:
185185
; GCN-DAG: v_readlane_b32 s30, [[CSR_VGPR]],
186186
; GCN: s_waitcnt vmcnt(0)
187187
; GCN: s_setpc_b64 s[30:31]
188-
call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 undef, i8 undef, float poison, float poison, float poison, i1 undef, <4 x i32> poison, float poison, i32 undef, i1 undef, i1 undef, i1 undef, float poison, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 undef, i1 undef, i32 undef, i64 undef, i32 undef)
188+
call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 poison, i8 undef, float poison, float poison, float poison, i1 undef, <4 x i32> poison, float poison, i32 poison, i1 undef, i1 undef, i1 undef, float poison, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 poison, i1 undef, i32 poison, i64 undef, i32 poison)
189189
ret void
190190
}
191191

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1
99
; NOPRIM: exp invalid_target_20 v0, off, off, off done{{$}}
1010
; PRIM: {{exp|export}} prim v0, off, off, off done{{$}}
1111
define amdgpu_gs void @test_export_prim_i32(i32 inreg %a) #0 {
12-
call void @llvm.amdgcn.exp.i32(i32 20, i32 1, i32 %a, i32 undef, i32 undef, i32 undef, i1 true, i1 false)
12+
call void @llvm.amdgcn.exp.i32(i32 20, i32 1, i32 %a, i32 poison, i32 poison, i32 poison, i1 true, i1 false)
1313
ret void
1414
}
1515

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -22,8 +22,8 @@ define amdgpu_kernel void @undef_i32() #0 {
2222
; GFX12-NEXT: export pos0 off, off, off, off row_en
2323
; GFX12-NEXT: export pos1 off, off, off, off done row_en
2424
; GFX12-NEXT: s_endpgm
25-
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i1 false, i32 0)
26-
call void @llvm.amdgcn.exp.row.i32(i32 13, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i1 true, i32 0)
25+
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i1 false, i32 0)
26+
call void @llvm.amdgcn.exp.row.i32(i32 13, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i1 true, i32 0)
2727
ret void
2828
}
2929

@@ -62,8 +62,8 @@ define amdgpu_kernel void @zero_i32() #0 {
6262
; GFX12-NEXT: export pos0 v0, v0, v0, off row_en
6363
; GFX12-NEXT: export pos1 v0, v0, v0, off done row_en
6464
; GFX12-NEXT: s_endpgm
65-
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 7, i32 0, i32 0, i32 0, i32 undef, i1 false, i32 0)
66-
call void @llvm.amdgcn.exp.row.i32(i32 13, i32 7, i32 0, i32 0, i32 0, i32 undef, i1 true, i32 0)
65+
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 7, i32 0, i32 0, i32 0, i32 poison, i1 false, i32 0)
66+
call void @llvm.amdgcn.exp.row.i32(i32 13, i32 7, i32 0, i32 0, i32 0, i32 poison, i1 true, i32 0)
6767
ret void
6868
}
6969

@@ -103,7 +103,7 @@ define amdgpu_kernel void @id_i32() #0 {
103103
; GFX12-NEXT: export pos0 v0, off, off, off done row_en
104104
; GFX12-NEXT: s_endpgm
105105
%id = call i32 @llvm.amdgcn.workitem.id.x()
106-
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 undef, i32 undef, i32 undef, i1 true, i32 0)
106+
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 poison, i32 poison, i32 poison, i1 true, i32 0)
107107
ret void
108108
}
109109

@@ -126,7 +126,7 @@ define amdgpu_kernel void @id_arg_i32(i32 %row) #0 {
126126
; GFX12-NEXT: export pos0 v0, off, off, off done row_en
127127
; GFX12-NEXT: s_endpgm
128128
%id = call i32 @llvm.amdgcn.workitem.id.x()
129-
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 undef, i32 undef, i32 undef, i1 true, i32 %row)
129+
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 poison, i32 poison, i32 poison, i1 true, i32 %row)
130130
ret void
131131
}
132132

@@ -170,6 +170,6 @@ define amdgpu_kernel void @id_row_i32() #0 {
170170
; GFX12-GISEL-NEXT: export pos0 v1, off, off, off done row_en
171171
; GFX12-GISEL-NEXT: s_endpgm
172172
%id = call i32 @llvm.amdgcn.workitem.id.x()
173-
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 99, i32 undef, i32 undef, i32 undef, i1 true, i32 %id)
173+
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 99, i32 poison, i32 poison, i32 poison, i1 true, i32 %id)
174174
ret void
175175
}

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
141141
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
142142
; GFX12-NEXT: ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
143143
bb:
144-
%i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 undef)
144+
%i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 poison)
145145
%i2 = call nsz arcp <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %arg, i32 %arg1, i32 0, i32 0, i32 0)
146146
%i3 = bitcast <3 x half> %i2 to <3 x i16>
147147
%i4 = extractelement <3 x i16> %i3, i32 1

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ define amdgpu_gs void @main(ptr addrspace(8) %arg, i32 %arg1) {
112112
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
113113
; GFX11-NEXT: ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
114114
bb:
115-
%i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 undef)
115+
%i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 poison)
116116
%i2 = call nsz arcp <3 x half> @llvm.amdgcn.struct.ptr.buffer.load.format.v3f16(ptr addrspace(8) %arg, i32 %arg1, i32 0, i32 0, i32 0)
117117
%i3 = bitcast <3 x half> %i2 to <3 x i16>
118118
%i4 = extractelement <3 x i16> %i3, i32 1

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ define i32 @test_s_wqm_constant_undef_i32() {
4242
; GFX11-NEXT: s_wqm_b32 s0, s0
4343
; GFX11-NEXT: v_mov_b32_e32 v0, s0
4444
; GFX11-NEXT: s_setpc_b64 s[30:31]
45-
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 undef)
45+
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 poison)
4646
ret i32 %br
4747
}
4848

‎llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ loop:
4646
br i1 %tmp27, label %then, label %endif
4747

4848
then: ; preds = %bb
49-
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
49+
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 poison, i32 0)
5050
br label %endif
5151

5252
endif: ; preds = %bb28, %bb
@@ -85,7 +85,7 @@ loop:
8585
%tmp23phi = phi i32 [ %tmp23, %loop ], [ 0, %entry ]
8686
%tmp23 = add nuw i32 %tmp23phi, 1
8787
%tmp27 = icmp ult i32 %arg, %tmp23
88-
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
88+
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 poison, i32 0)
8989
br i1 %tmp27, label %loop, label %loopexit
9090

9191
loopexit:
@@ -136,7 +136,7 @@ loop:
136136
br i1 %tmp27, label %then, label %endif
137137

138138
then: ; preds = %bb
139-
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
139+
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 poison, i32 0)
140140
br label %endif
141141

142142
endif: ; preds = %bb28, %bb

‎llvm/test/CodeGen/AMDGPU/merge-load-store.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,8 @@
3434
bb:
3535
%tmp1 = load i32, i32 addrspace(3)* getelementptr inbounds ([256 x i32], [256 x i32] addrspace(3)* @lds0, i32 0, i32 0), align 4
3636
%0 = and i32 %tmp1, 255
37-
%tmp3 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 undef), align 4
38-
%tmp6 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 undef), align 4
37+
%tmp3 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 poison), align 4
38+
%tmp6 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 poison), align 4
3939
%tmp7 = tail call i32 asm "v_or_b32 $0, 0, $1", "=v,v"(i32 %tmp6) #1
4040
%tmp10 = lshr i32 %tmp7, 16
4141
%tmp11 = and i32 %tmp10, 255
@@ -48,7 +48,7 @@
4848
%tmp20 = and i32 %tmp19, 255
4949
%tmp21 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 %tmp20
5050
%tmp22 = load i32, i32 addrspace(3)* %tmp21, align 4
51-
%tmp24 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 undef), align 4
51+
%tmp24 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 poison), align 4
5252
%tmp25 = xor i32 %tmp22, %tmp24
5353
%tmp26 = and i32 %tmp25, -16777216
5454
%tmp28 = or i32 %0, %tmp26
@@ -129,12 +129,12 @@ body: |
129129
bb.0:
130130
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
131131
%2:vgpr_32 = DS_READ_B32 %1, 3072, 0, implicit $m0, implicit $exec :: (dereferenceable load (s32) from `i32 addrspace(3)* getelementptr inbounds ([256 x i32], [256 x i32] addrspace(3)* @lds0, i32 0, i32 0)`, addrspace 3)
132-
%3:vgpr_32 = DS_READ_B32 %1, 2048, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 undef)`, addrspace 3)
133-
%4:vgpr_32 = DS_READ_B32 %1, 1024, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 undef)`, addrspace 3)
132+
%3:vgpr_32 = DS_READ_B32 %1, 2048, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 poison)`, addrspace 3)
133+
%4:vgpr_32 = DS_READ_B32 %1, 1024, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 poison)`, addrspace 3)
134134
INLINEASM &"v_or_b32 $0, 0, $1", 32, 327690, def %0, 327689, %4
135135
%5:vgpr_32 = DS_READ_B32 %0, 2048, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp12, addrspace 3)
136136
%6:vgpr_32 = DS_READ_B32 %5, 2048, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp21, addrspace 3)
137-
%7:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 undef)`, addrspace 3)
137+
%7:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 poison)`, addrspace 3)
138138
S_SETPC_B64_return undef $sgpr30_sgpr31, implicit %6, implicit %7
139139
140140
...

‎llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ define amdgpu_vs float @test_idxen(ptr addrspace(4) inreg %base, i32 %i) {
2222
main_body:
2323
%ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
2424
%tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
25-
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i32 0, i32 0)
25+
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 poison, i32 0, i32 0, i32 0)
2626
ret float %tmp7
2727
}
2828

@@ -32,7 +32,7 @@ define amdgpu_vs float @test_offen(ptr addrspace(4) inreg %base, i32 %i) {
3232
main_body:
3333
%ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
3434
%tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
35-
%tmp7 = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i32 0)
35+
%tmp7 = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %tmp2, i32 poison, i32 0, i32 0)
3636
ret float %tmp7
3737
}
3838

@@ -42,7 +42,7 @@ define amdgpu_vs float @test_both(ptr addrspace(4) inreg %base, i32 %i) {
4242
main_body:
4343
%ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
4444
%tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
45-
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 undef, i32 0, i32 0)
45+
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 poison, i32 poison, i32 0, i32 0)
4646
ret float %tmp7
4747
}
4848

‎llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ define amdgpu_vs float @test_idxen(ptr addrspace(4) inreg %base, i32 %i) {
1919
main_body:
2020
%ptr = getelementptr ptr addrspace(8), ptr addrspace(4) %base, i32 %i
2121
%tmp2 = load ptr addrspace(8), ptr addrspace(4) %ptr, align 32
22-
%tmp7 = call float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 undef, i32 0, i32 0, i32 0)
22+
%tmp7 = call float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 poison, i32 0, i32 0, i32 0)
2323
ret float %tmp7
2424
}
2525

@@ -29,7 +29,7 @@ define amdgpu_vs float @test_offen(ptr addrspace(4) inreg %base, i32 %i) {
2929
main_body:
3030
%ptr = getelementptr ptr addrspace(8), ptr addrspace(4) %base, i32 %i
3131
%tmp2 = load ptr addrspace(8), ptr addrspace(4) %ptr, align 32
32-
%tmp7 = call float @llvm.amdgcn.raw.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 undef, i32 0, i32 0)
32+
%tmp7 = call float @llvm.amdgcn.raw.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 poison, i32 0, i32 0)
3333
ret float %tmp7
3434
}
3535

@@ -39,7 +39,7 @@ define amdgpu_vs float @test_both(ptr addrspace(4) inreg %base, i32 %i) {
3939
main_body:
4040
%ptr = getelementptr ptr addrspace(8), ptr addrspace(4) %base, i32 %i
4141
%tmp2 = load ptr addrspace(8), ptr addrspace(4) %ptr, align 32
42-
%tmp7 = call float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 undef, i32 undef, i32 0, i32 0)
42+
%tmp7 = call float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 poison, i32 poison, i32 0, i32 0)
4343
ret float %tmp7
4444
}
4545

‎llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
9292
; PEI-GFX90A-NEXT: GLOBAL_STORE_DWORDX2 undef renamable $vgpr0_vgpr1, killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec :: (volatile store (s64) into `ptr addrspace(1) poison`, addrspace 1)
9393
; PEI-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef renamable $vgpr0_vgpr1, killed renamable $agpr0_agpr1_agpr2_agpr3, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
9494
; PEI-GFX90A-NEXT: S_ENDPGM 0
95-
call void asm sideeffect "; use $0", "a" (i32 undef)
95+
call void asm sideeffect "; use $0", "a" (i32 poison)
9696
%v0 = call <4 x i32> asm sideeffect "; def $0", "=v" ()
9797
%v1 = call <2 x i32> asm sideeffect "; def $0", "=v" ()
9898
%mai = tail call <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32 1, i32 2, <4 x i32> %arg, i32 0, i32 0, i32 0)

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