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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| 2 | +; RUN: opt -mtriple=riscv64 -mcpu=sifive-x280 -passes=slp-vectorizer -S -slp-revec -slp-max-reg-size=1024 -slp-threshold=-10 -pass-remarks-output=%t %s | FileCheck %s |
| 3 | +; RUN: FileCheck --input-file=%t --check-prefix=YAML %s |
| 4 | + |
| 5 | +; YAML: --- !Passed |
| 6 | +; YAML: Pass: slp-vectorizer |
| 7 | +; YAML: Name: StoresVectorized |
| 8 | +; YAML: Function: test |
| 9 | +; YAML: Args: |
| 10 | +; YAML: - String: 'Stores SLP vectorized with cost ' |
| 11 | +; YAML: - Cost: '6' |
| 12 | +; YAML: - String: ' and with tree size ' |
| 13 | +; YAML: - TreeSize: '5' |
| 14 | + |
| 15 | +define void @test(<4 x float> %load6, <4 x float> %load7, <4 x float> %load8, <4 x float> %load17, <4 x float> %fmuladd7, <4 x float> %fmuladd16, ptr %out_ptr) { |
| 16 | +; CHECK-LABEL: @test( |
| 17 | +; CHECK-NEXT: entry: |
| 18 | +; CHECK-NEXT: [[VEXT165_I:%.*]] = shufflevector <4 x float> [[LOAD6:%.*]], <4 x float> [[LOAD7:%.*]], <4 x i32> <i32 2, i32 3, i32 4, i32 5> |
| 19 | +; CHECK-NEXT: [[VEXT309_I:%.*]] = shufflevector <4 x float> [[LOAD7]], <4 x float> [[LOAD8:%.*]], <4 x i32> <i32 2, i32 3, i32 4, i32 5> |
| 20 | +; CHECK-NEXT: [[TMP0:%.*]] = call <8 x float> @llvm.vector.insert.v8f32.v4f32(<8 x float> poison, <4 x float> [[VEXT165_I]], i64 0) |
| 21 | +; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.vector.insert.v8f32.v4f32(<8 x float> [[TMP0]], <4 x float> [[VEXT309_I]], i64 4) |
| 22 | +; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.vector.insert.v8f32.v4f32(<8 x float> poison, <4 x float> poison, i64 4) |
| 23 | +; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.vector.insert.v8f32.v4f32(<8 x float> [[TMP2]], <4 x float> [[LOAD17:%.*]], i64 0) |
| 24 | +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> |
| 25 | +; CHECK-NEXT: [[TMP5:%.*]] = call <8 x float> @llvm.vector.insert.v8f32.v4f32(<8 x float> poison, <4 x float> [[FMULADD7:%.*]], i64 0) |
| 26 | +; CHECK-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.vector.insert.v8f32.v4f32(<8 x float> [[TMP5]], <4 x float> [[FMULADD16:%.*]], i64 4) |
| 27 | +; CHECK-NEXT: [[TMP7:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP4]], <8 x float> [[TMP6]]) |
| 28 | +; CHECK-NEXT: store <8 x float> [[TMP7]], ptr [[OUT_PTR:%.*]], align 4 |
| 29 | +; CHECK-NEXT: ret void |
| 30 | +; |
| 31 | +entry: |
| 32 | + %vext165.i = shufflevector <4 x float> %load6, <4 x float> %load7, <4 x i32> <i32 2, i32 3, i32 4, i32 5> |
| 33 | + %vext309.i = shufflevector <4 x float> %load7, <4 x float> %load8, <4 x i32> <i32 2, i32 3, i32 4, i32 5> |
| 34 | + %fmuladd8 = tail call noundef <4 x float> @llvm.fmuladd.v4f32(<4 x float> %vext165.i, <4 x float> %load17, <4 x float> %fmuladd7) |
| 35 | + %fmuladd17 = tail call noundef <4 x float> @llvm.fmuladd.v4f32(<4 x float> %vext309.i, <4 x float> %load17, <4 x float> %fmuladd16) |
| 36 | + %add.ptr.i.i = getelementptr inbounds i8, ptr %out_ptr, i64 16 |
| 37 | + store <4 x float> %fmuladd8, ptr %out_ptr, align 4 |
| 38 | + store <4 x float> %fmuladd17, ptr %add.ptr.i.i, align 4 |
| 39 | + ret void |
| 40 | +} |
| 41 | + |
| 42 | +declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) |
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