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[AMDGPU] Rename getNumVGPRBlocks. NFC (#84161)
Rename getNumVGPRBlocks to getEncodedNumVGPRBlocks, to clarify that it's using the encoding granule. This is used to program the hardware. In practice, the hardware will use the alloc granule instead, so this patch also adds a new helper, getAllocatedNumVGPRBlocks, which can be useful when driving heuristics.
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4 files changed

+33
-16
lines changed

4 files changed

+33
-16
lines changed

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -868,8 +868,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
868868

869869
ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks(
870870
&STM, ProgInfo.NumSGPRsForWavesPerEU);
871-
ProgInfo.VGPRBlocks = IsaInfo::getNumVGPRBlocks(
872-
&STM, ProgInfo.NumVGPRsForWavesPerEU);
871+
ProgInfo.VGPRBlocks =
872+
IsaInfo::getEncodedNumVGPRBlocks(&STM, ProgInfo.NumVGPRsForWavesPerEU);
873873

874874
const SIModeRegisterDefaults Mode = MFI->getMode();
875875

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5344,8 +5344,8 @@ bool AMDGPUAsmParser::calculateGPRBlocks(
53445344
NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
53455345
}
53465346

5347-
VGPRBlocks =
5348-
IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);
5347+
VGPRBlocks = IsaInfo::getEncodedNumVGPRBlocks(&getSTI(), NumVGPRs,
5348+
EnableWavefrontSize32);
53495349
SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);
53505350

53515351
return false;

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 18 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1060,10 +1060,15 @@ unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
10601060
STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
10611061
}
10621062

1063+
static unsigned getGranulatedNumRegisterBlocks(unsigned NumRegs,
1064+
unsigned Granule) {
1065+
return divideCeil(std::max(1u, NumRegs), Granule);
1066+
}
1067+
10631068
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
1064-
NumSGPRs = alignTo(std::max(1u, NumSGPRs), getSGPREncodingGranule(STI));
10651069
// SGPRBlocks is actual number of SGPR blocks minus 1.
1066-
return NumSGPRs / getSGPREncodingGranule(STI) - 1;
1070+
return getGranulatedNumRegisterBlocks(NumSGPRs, getSGPREncodingGranule(STI)) -
1071+
1;
10671072
}
10681073

10691074
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
@@ -1158,14 +1163,19 @@ unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
11581163
return std::min(MaxNumVGPRs, AddressableNumVGPRs);
11591164
}
11601165

1161-
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
1162-
std::optional<bool> EnableWavefrontSize32) {
1163-
NumVGPRs = alignTo(std::max(1u, NumVGPRs),
1164-
getVGPREncodingGranule(STI, EnableWavefrontSize32));
1165-
// VGPRBlocks is actual number of VGPR blocks minus 1.
1166-
return NumVGPRs / getVGPREncodingGranule(STI, EnableWavefrontSize32) - 1;
1166+
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
1167+
std::optional<bool> EnableWavefrontSize32) {
1168+
return getGranulatedNumRegisterBlocks(
1169+
NumVGPRs, getVGPREncodingGranule(STI, EnableWavefrontSize32)) -
1170+
1;
11671171
}
11681172

1173+
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI,
1174+
unsigned NumVGPRs,
1175+
std::optional<bool> EnableWavefrontSize32) {
1176+
return getGranulatedNumRegisterBlocks(
1177+
NumVGPRs, getVGPRAllocGranule(STI, EnableWavefrontSize32));
1178+
}
11691179
} // end namespace IsaInfo
11701180

11711181
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -316,13 +316,20 @@ unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI,
316316
unsigned NumVGPRs);
317317

318318
/// \returns Number of VGPR blocks needed for given subtarget \p STI when
319-
/// \p NumVGPRs are used.
319+
/// \p NumVGPRs are used. We actually return the number of blocks -1, since
320+
/// that's what we encode.
320321
///
321322
/// For subtargets which support it, \p EnableWavefrontSize32 should match the
322323
/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
323-
unsigned
324-
getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
325-
std::optional<bool> EnableWavefrontSize32 = std::nullopt);
324+
unsigned getEncodedNumVGPRBlocks(
325+
const MCSubtargetInfo *STI, unsigned NumVGPRs,
326+
std::optional<bool> EnableWavefrontSize32 = std::nullopt);
327+
328+
/// \returns Number of VGPR blocks that need to be allocated for the given
329+
/// subtarget \p STI when \p NumVGPRs are used.
330+
unsigned getAllocatedNumVGPRBlocks(
331+
const MCSubtargetInfo *STI, unsigned NumVGPRs,
332+
std::optional<bool> EnableWavefrontSize32 = std::nullopt);
326333

327334
} // end namespace IsaInfo
328335

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