Skip to content

Commit 00ae6bb

Browse files
committed
[ARM] Regenerate MIR test (NFC)
1 parent b6240c3 commit 00ae6bb

File tree

1 file changed

+61
-43
lines changed

1 file changed

+61
-43
lines changed

llvm/test/CodeGen/ARM/constant-islands-split-IT.mir

Lines changed: 61 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
#
77

88
--- |
9-
; ModuleID = '<stdin>'
109
source_filename = "<stdin>"
1110
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
1211
target triple = "thumbv8m.main-arm-none-eabi"
@@ -69,48 +68,67 @@ machineFunctionInfo: {}
6968
body: |
7069
; CHECK-LABEL: name: h
7170
; CHECK: bb.0:
72-
; CHECK: successors: %bb.4(0x80000000)
73-
; CHECK: renamable $d0 = VLDRD %const.3, 0, 14 /* CC::al */, $noreg :: (load (s64) from constant-pool)
74-
; CHECK: dead renamable $r0 = SPACE 40, undef renamable $r0
75-
; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
76-
; CHECK: bb.1 (align 8):
77-
; CHECK: successors:
78-
; CHECK: CONSTPOOL_ENTRY 3, %const.0, 8
79-
; CHECK: bb.2:
80-
; CHECK: successors:
81-
; CHECK: bb.3 (align 8):
82-
; CHECK: successors:
83-
; CHECK: CONSTPOOL_ENTRY 5, %const.2, 8
84-
; CHECK: bb.4 (align 2):
85-
; CHECK: successors: %bb.5(0x80000000)
86-
; CHECK: dead renamable $r0 = SPACE 790, undef renamable $r0
87-
; CHECK: bb.5:
88-
; CHECK: successors: %bb.7(0x80000000)
89-
; CHECK: renamable $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
90-
; CHECK: t2CMPri $r0, 32, 14 /* CC::al */, $noreg, implicit-def $cpsr
91-
; CHECK: renamable $r0 = SPACE 200, undef renamable $r0
92-
; CHECK: t2IT 0, 1, implicit-def $itstate
93-
; CHECK: renamable $d0 = VLDRD %const.7, 0, 0 /* CC::eq */, $cpsr, implicit $itstate :: (load (s64) from constant-pool)
94-
; CHECK: renamable $d1 = VLDRD %const.5, 0, 0 /* CC::eq */, $cpsr, implicit $itstate :: (load (s64) from constant-pool)
95-
; CHECK: renamable $d2 = VLDRD %const.6, 0, 0 /* CC::eq */, $cpsr, implicit $itstate :: (load (s64) from constant-pool)
96-
; CHECK: $r0 = t2SUBri $r0, 12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $itstate
97-
; CHECK: t2B %bb.7, 14 /* CC::al */, $noreg
98-
; CHECK: bb.6 (align 8):
99-
; CHECK: successors:
100-
; CHECK: CONSTPOOL_ENTRY 7, %const.1, 8
101-
; CHECK: bb.7 (align 2):
102-
; CHECK: liveins: $r0, $cpsr, $d0, $s0, $s1, $d1, $s2, $s3, $d2, $s4, $s5
103-
; CHECK: t2IT 0, 4, implicit-def $itstate
104-
; CHECK: $sp = tMOVr $r0, 0 /* CC::eq */, $cpsr, implicit $itstate
105-
; CHECK: $sp = t2LDMIA_RET $sp, 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate
106-
; CHECK: bb.8 (align 8):
107-
; CHECK: successors:
108-
; CHECK: CONSTPOOL_ENTRY 6, %const.0, 8
109-
; CHECK: bb.9 (align 2):
110-
; CHECK: successors: %bb.9(0x80000000)
111-
; CHECK: dead renamable $r0 = SPACE 4000, undef renamable $r0
112-
; CHECK: t2B %bb.9, 14 /* CC::al */, $noreg
113-
; CHECK: bb.10:
71+
; CHECK-NEXT: successors: %bb.4(0x80000000)
72+
; CHECK-NEXT: {{ $}}
73+
; CHECK-NEXT: renamable $d0 = VLDRD %const.3, 0, 14 /* CC::al */, $noreg :: (load (s64) from constant-pool)
74+
; CHECK-NEXT: dead renamable $r0 = SPACE 40, undef renamable $r0
75+
; CHECK-NEXT: tB %bb.4, 14 /* CC::al */, $noreg
76+
; CHECK-NEXT: {{ $}}
77+
; CHECK-NEXT: bb.1 (align 8):
78+
; CHECK-NEXT: successors:
79+
; CHECK-NEXT: {{ $}}
80+
; CHECK-NEXT: CONSTPOOL_ENTRY 3, %const.0, 8
81+
; CHECK-NEXT: {{ $}}
82+
; CHECK-NEXT: bb.2:
83+
; CHECK-NEXT: successors:
84+
; CHECK-NEXT: {{ $}}
85+
; CHECK-NEXT: bb.3 (align 8):
86+
; CHECK-NEXT: successors:
87+
; CHECK-NEXT: {{ $}}
88+
; CHECK-NEXT: CONSTPOOL_ENTRY 5, %const.2, 8
89+
; CHECK-NEXT: {{ $}}
90+
; CHECK-NEXT: bb.4 (align 2):
91+
; CHECK-NEXT: successors: %bb.5(0x80000000)
92+
; CHECK-NEXT: {{ $}}
93+
; CHECK-NEXT: dead renamable $r0 = SPACE 790, undef renamable $r0
94+
; CHECK-NEXT: {{ $}}
95+
; CHECK-NEXT: bb.5:
96+
; CHECK-NEXT: successors: %bb.7(0x80000000)
97+
; CHECK-NEXT: {{ $}}
98+
; CHECK-NEXT: renamable $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
99+
; CHECK-NEXT: t2CMPri $r0, 32, 14 /* CC::al */, $noreg, implicit-def $cpsr
100+
; CHECK-NEXT: renamable $r0 = SPACE 200, undef renamable $r0
101+
; CHECK-NEXT: t2IT 0, 1, implicit-def $itstate
102+
; CHECK-NEXT: renamable $d0 = VLDRD %const.7, 0, 0 /* CC::eq */, $cpsr, implicit $itstate :: (load (s64) from constant-pool)
103+
; CHECK-NEXT: renamable $d1 = VLDRD %const.5, 0, 0 /* CC::eq */, $cpsr, implicit $itstate :: (load (s64) from constant-pool)
104+
; CHECK-NEXT: renamable $d2 = VLDRD %const.6, 0, 0 /* CC::eq */, $cpsr, implicit $itstate :: (load (s64) from constant-pool)
105+
; CHECK-NEXT: $r0 = t2SUBri $r0, 12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $itstate
106+
; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg
107+
; CHECK-NEXT: {{ $}}
108+
; CHECK-NEXT: bb.6 (align 8):
109+
; CHECK-NEXT: successors:
110+
; CHECK-NEXT: {{ $}}
111+
; CHECK-NEXT: CONSTPOOL_ENTRY 7, %const.1, 8
112+
; CHECK-NEXT: {{ $}}
113+
; CHECK-NEXT: bb.7 (align 2):
114+
; CHECK-NEXT: liveins: $r0, $cpsr, $d0, $s0, $s1, $d1, $s2, $s3, $d2, $s4, $s5
115+
; CHECK-NEXT: {{ $}}
116+
; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate
117+
; CHECK-NEXT: $sp = tMOVr $r0, 0 /* CC::eq */, $cpsr, implicit $itstate
118+
; CHECK-NEXT: $sp = t2LDMIA_RET $sp, 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate
119+
; CHECK-NEXT: {{ $}}
120+
; CHECK-NEXT: bb.8 (align 8):
121+
; CHECK-NEXT: successors:
122+
; CHECK-NEXT: {{ $}}
123+
; CHECK-NEXT: CONSTPOOL_ENTRY 6, %const.0, 8
124+
; CHECK-NEXT: {{ $}}
125+
; CHECK-NEXT: bb.9 (align 2):
126+
; CHECK-NEXT: successors: %bb.9(0x80000000)
127+
; CHECK-NEXT: {{ $}}
128+
; CHECK-NEXT: dead renamable $r0 = SPACE 4000, undef renamable $r0
129+
; CHECK-NEXT: t2B %bb.9, 14 /* CC::al */, $noreg
130+
; CHECK-NEXT: {{ $}}
131+
; CHECK-NEXT: bb.10:
114132
bb.0:
115133
successors: %bb.1(0x80000000)
116134

0 commit comments

Comments
 (0)