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Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
The original change had a bug where it allowed SEW mutation. This is wrong in multiple ways, but an easy example is that the slide amount is in units of SEW, and thus that changing SEW changes the slide offset. I'd reverted this in 3331469 intending to more majorly rework the patch because in addition to the bug, I'd noticed a potential oppurtunity to increase scope. After implementing that variant, and realizing it triggered nowhere, I decided to go back to the prior patch with the minimal fix. Note there's no separate test case for the fix. This is because we already had multiple, and I just didn't realize the impact of the original test diff. Adding one more test would have been unlikely to catch that human error. Original commit message.. Noticed this while looking at some SLP output. If we have an extractelement, we're probably using a slidedown into an destination with no contents. Given this, we can allow the slideup to use a larger VL and clobber tail elements of the destination vector. Doing this allows us to avoid vsetvli toggles in many fixed length vector examples. Differential Revision: https://reviews.llvm.org/D148834
1 parent 617c9d5 commit 020812b

16 files changed

+109
-226
lines changed

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,18 @@ static bool isScalarMoveInstr(const MachineInstr &MI) {
8585
}
8686
}
8787

88+
static bool isVSlideInstr(const MachineInstr &MI) {
89+
switch (getRVVMCOpcode(MI.getOpcode())) {
90+
default:
91+
return false;
92+
case RISCV::VSLIDEDOWN_VX:
93+
case RISCV::VSLIDEDOWN_VI:
94+
case RISCV::VSLIDEUP_VX:
95+
case RISCV::VSLIDEUP_VI:
96+
return true;
97+
}
98+
}
99+
88100
/// Get the EEW for a load or store instruction. Return std::nullopt if MI is
89101
/// not a load or store which ignores SEW.
90102
static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
@@ -818,6 +830,11 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
818830
.addImm(Info.encodeVTYPE());
819831
}
820832

833+
static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL) {
834+
auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL);
835+
return Fractional || LMul == 1;
836+
}
837+
821838
/// Return true if a VSETVLI is required to transition from CurInfo to Require
822839
/// before MI.
823840
bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
@@ -845,6 +862,25 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
845862
}
846863
}
847864

865+
// A slidedown/slideup with an IMPLICIT_DEF merge op can freely clobber
866+
// elements not copied from the source vector (e.g. masked off, tail, or
867+
// slideup's prefix). Notes:
868+
// * We can't modify SEW here since the slide amount is in units of SEW.
869+
// * VL=1 is special only because we have existing support for zero vs
870+
// non-zero VL. We could generalize this if we had a VL > C predicate.
871+
// * The LMUL1 restriction is for machines whose latency may depend on VL.
872+
// * As above, this is only legal for IMPLICIT_DEF, not TA.
873+
if (isVSlideInstr(MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
874+
isLMUL1OrSmaller(CurInfo.getVLMUL())) {
875+
auto *VRegDef = MRI->getVRegDef(MI.getOperand(1).getReg());
876+
if (VRegDef && VRegDef->isImplicitDef()) {
877+
Used.VLAny = false;
878+
Used.VLZeroness = true;
879+
Used.LMUL = false;
880+
Used.TailPolicy = false;
881+
}
882+
}
883+
848884
if (CurInfo.isCompatible(Used, Require))
849885
return false;
850886

‎llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@ define i1 @extractelt_nxv1i1(<vscale x 1 x i8>* %x, i64 %idx) nounwind {
1010
; CHECK-NEXT: vmseq.vi v0, v8, 0
1111
; CHECK-NEXT: vmv.v.i v8, 0
1212
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
13-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
1413
; CHECK-NEXT: vslidedown.vx v8, v8, a1
1514
; CHECK-NEXT: vmv.x.s a0, v8
1615
; CHECK-NEXT: ret
@@ -28,7 +27,6 @@ define i1 @extractelt_nxv2i1(<vscale x 2 x i8>* %x, i64 %idx) nounwind {
2827
; CHECK-NEXT: vmseq.vi v0, v8, 0
2928
; CHECK-NEXT: vmv.v.i v8, 0
3029
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
31-
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
3230
; CHECK-NEXT: vslidedown.vx v8, v8, a1
3331
; CHECK-NEXT: vmv.x.s a0, v8
3432
; CHECK-NEXT: ret
@@ -46,7 +44,6 @@ define i1 @extractelt_nxv4i1(<vscale x 4 x i8>* %x, i64 %idx) nounwind {
4644
; CHECK-NEXT: vmseq.vi v0, v8, 0
4745
; CHECK-NEXT: vmv.v.i v8, 0
4846
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
49-
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
5047
; CHECK-NEXT: vslidedown.vx v8, v8, a1
5148
; CHECK-NEXT: vmv.x.s a0, v8
5249
; CHECK-NEXT: ret
@@ -64,7 +61,6 @@ define i1 @extractelt_nxv8i1(<vscale x 8 x i8>* %x, i64 %idx) nounwind {
6461
; CHECK-NEXT: vmseq.vi v0, v8, 0
6562
; CHECK-NEXT: vmv.v.i v8, 0
6663
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
67-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
6864
; CHECK-NEXT: vslidedown.vx v8, v8, a1
6965
; CHECK-NEXT: vmv.x.s a0, v8
7066
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,7 @@ define <2 x i1> @reverse_v2i1(<2 x i1> %a) {
1616
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
1717
; CHECK-NEXT: vmv.v.i v8, 0
1818
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
19-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
2019
; CHECK-NEXT: vslidedown.vi v9, v8, 1
21-
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
2220
; CHECK-NEXT: vslideup.vi v9, v8, 1
2321
; CHECK-NEXT: vmsne.vi v0, v9, 0
2422
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,6 @@ define i1 @extractelt_v2i1(ptr %x, i64 %idx) nounwind {
3030
; CHECK-NEXT: vmseq.vi v0, v8, 0
3131
; CHECK-NEXT: vmv.v.i v8, 0
3232
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
33-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
3433
; CHECK-NEXT: vslidedown.vx v8, v8, a1
3534
; CHECK-NEXT: vmv.x.s a0, v8
3635
; CHECK-NEXT: ret
@@ -48,7 +47,6 @@ define i1 @extractelt_v4i1(ptr %x, i64 %idx) nounwind {
4847
; CHECK-NEXT: vmseq.vi v0, v8, 0
4948
; CHECK-NEXT: vmv.v.i v8, 0
5049
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
51-
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
5250
; CHECK-NEXT: vslidedown.vx v8, v8, a1
5351
; CHECK-NEXT: vmv.x.s a0, v8
5452
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

Lines changed: 7 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@ define i8 @extractelt_v16i8(ptr %x) nounwind {
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1111
; CHECK-NEXT: vle8.v v8, (a0)
12-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1312
; CHECK-NEXT: vslidedown.vi v8, v8, 7
1413
; CHECK-NEXT: vmv.x.s a0, v8
1514
; CHECK-NEXT: ret
@@ -23,7 +22,6 @@ define i16 @extractelt_v8i16(ptr %x) nounwind {
2322
; CHECK: # %bb.0:
2423
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
2524
; CHECK-NEXT: vle16.v v8, (a0)
26-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
2725
; CHECK-NEXT: vslidedown.vi v8, v8, 7
2826
; CHECK-NEXT: vmv.x.s a0, v8
2927
; CHECK-NEXT: ret
@@ -37,7 +35,6 @@ define i32 @extractelt_v4i32(ptr %x) nounwind {
3735
; CHECK: # %bb.0:
3836
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
3937
; CHECK-NEXT: vle32.v v8, (a0)
40-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
4138
; CHECK-NEXT: vslidedown.vi v8, v8, 2
4239
; CHECK-NEXT: vmv.x.s a0, v8
4340
; CHECK-NEXT: ret
@@ -74,7 +71,6 @@ define half @extractelt_v8f16(ptr %x) nounwind {
7471
; CHECK: # %bb.0:
7572
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
7673
; CHECK-NEXT: vle16.v v8, (a0)
77-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
7874
; CHECK-NEXT: vslidedown.vi v8, v8, 7
7975
; CHECK-NEXT: vfmv.f.s fa0, v8
8076
; CHECK-NEXT: ret
@@ -88,7 +84,6 @@ define float @extractelt_v4f32(ptr %x) nounwind {
8884
; CHECK: # %bb.0:
8985
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
9086
; CHECK-NEXT: vle32.v v8, (a0)
91-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
9287
; CHECK-NEXT: vslidedown.vi v8, v8, 2
9388
; CHECK-NEXT: vfmv.f.s fa0, v8
9489
; CHECK-NEXT: ret
@@ -252,7 +247,6 @@ define i8 @extractelt_v16i8_idx(ptr %x, i32 zeroext %idx) nounwind {
252247
; CHECK: # %bb.0:
253248
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
254249
; CHECK-NEXT: vle8.v v8, (a0)
255-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
256250
; CHECK-NEXT: vslidedown.vx v8, v8, a1
257251
; CHECK-NEXT: vmv.x.s a0, v8
258252
; CHECK-NEXT: ret
@@ -266,7 +260,6 @@ define i16 @extractelt_v8i16_idx(ptr %x, i32 zeroext %idx) nounwind {
266260
; CHECK: # %bb.0:
267261
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
268262
; CHECK-NEXT: vle16.v v8, (a0)
269-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
270263
; CHECK-NEXT: vslidedown.vx v8, v8, a1
271264
; CHECK-NEXT: vmv.x.s a0, v8
272265
; CHECK-NEXT: ret
@@ -281,7 +274,6 @@ define i32 @extractelt_v4i32_idx(ptr %x, i32 zeroext %idx) nounwind {
281274
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
282275
; CHECK-NEXT: vle32.v v8, (a0)
283276
; CHECK-NEXT: vadd.vv v8, v8, v8
284-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
285277
; CHECK-NEXT: vslidedown.vx v8, v8, a1
286278
; CHECK-NEXT: vmv.x.s a0, v8
287279
; CHECK-NEXT: ret
@@ -297,10 +289,10 @@ define i64 @extractelt_v2i64_idx(ptr %x, i32 zeroext %idx) nounwind {
297289
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
298290
; RV32-NEXT: vle64.v v8, (a0)
299291
; RV32-NEXT: vadd.vv v8, v8, v8
300-
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
301292
; RV32-NEXT: vslidedown.vx v8, v8, a1
302293
; RV32-NEXT: vmv.x.s a0, v8
303294
; RV32-NEXT: li a1, 32
295+
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
304296
; RV32-NEXT: vsrl.vx v8, v8, a1
305297
; RV32-NEXT: vmv.x.s a1, v8
306298
; RV32-NEXT: ret
@@ -310,7 +302,6 @@ define i64 @extractelt_v2i64_idx(ptr %x, i32 zeroext %idx) nounwind {
310302
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
311303
; RV64-NEXT: vle64.v v8, (a0)
312304
; RV64-NEXT: vadd.vv v8, v8, v8
313-
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
314305
; RV64-NEXT: vslidedown.vx v8, v8, a1
315306
; RV64-NEXT: vmv.x.s a0, v8
316307
; RV64-NEXT: ret
@@ -326,7 +317,6 @@ define half @extractelt_v8f16_idx(ptr %x, i32 zeroext %idx) nounwind {
326317
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
327318
; CHECK-NEXT: vle16.v v8, (a0)
328319
; CHECK-NEXT: vfadd.vv v8, v8, v8
329-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
330320
; CHECK-NEXT: vslidedown.vx v8, v8, a1
331321
; CHECK-NEXT: vfmv.f.s fa0, v8
332322
; CHECK-NEXT: ret
@@ -342,7 +332,6 @@ define float @extractelt_v4f32_idx(ptr %x, i32 zeroext %idx) nounwind {
342332
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
343333
; CHECK-NEXT: vle32.v v8, (a0)
344334
; CHECK-NEXT: vfadd.vv v8, v8, v8
345-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
346335
; CHECK-NEXT: vslidedown.vx v8, v8, a1
347336
; CHECK-NEXT: vfmv.f.s fa0, v8
348337
; CHECK-NEXT: ret
@@ -358,7 +347,6 @@ define double @extractelt_v2f64_idx(ptr %x, i32 zeroext %idx) nounwind {
358347
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
359348
; CHECK-NEXT: vle64.v v8, (a0)
360349
; CHECK-NEXT: vfadd.vv v8, v8, v8
361-
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
362350
; CHECK-NEXT: vslidedown.vx v8, v8, a1
363351
; CHECK-NEXT: vfmv.f.s fa0, v8
364352
; CHECK-NEXT: ret
@@ -529,8 +517,8 @@ define void @store_extractelt_v16i8(ptr %x, ptr %p) nounwind {
529517
; CHECK: # %bb.0:
530518
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
531519
; CHECK-NEXT: vle8.v v8, (a0)
532-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
533520
; CHECK-NEXT: vslidedown.vi v8, v8, 7
521+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
534522
; CHECK-NEXT: vse8.v v8, (a1)
535523
; CHECK-NEXT: ret
536524
%a = load <16 x i8>, ptr %x
@@ -544,8 +532,8 @@ define void @store_extractelt_v8i16(ptr %x, ptr %p) nounwind {
544532
; CHECK: # %bb.0:
545533
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
546534
; CHECK-NEXT: vle16.v v8, (a0)
547-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
548535
; CHECK-NEXT: vslidedown.vi v8, v8, 7
536+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
549537
; CHECK-NEXT: vse16.v v8, (a1)
550538
; CHECK-NEXT: ret
551539
%a = load <8 x i16>, ptr %x
@@ -559,8 +547,8 @@ define void @store_extractelt_v4i32(ptr %x, ptr %p) nounwind {
559547
; CHECK: # %bb.0:
560548
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
561549
; CHECK-NEXT: vle32.v v8, (a0)
562-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
563550
; CHECK-NEXT: vslidedown.vi v8, v8, 2
551+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
564552
; CHECK-NEXT: vse32.v v8, (a1)
565553
; CHECK-NEXT: ret
566554
%a = load <4 x i32>, ptr %x
@@ -575,9 +563,9 @@ define void @store_extractelt_v2i64(ptr %x, ptr %p) nounwind {
575563
; RV32: # %bb.0:
576564
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
577565
; RV32-NEXT: vle64.v v8, (a0)
578-
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
579566
; RV32-NEXT: vslidedown.vi v8, v8, 1
580567
; RV32-NEXT: li a0, 32
568+
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
581569
; RV32-NEXT: vsrl.vx v9, v8, a0
582570
; RV32-NEXT: vmv.x.s a0, v9
583571
; RV32-NEXT: vmv.x.s a2, v8
@@ -589,8 +577,8 @@ define void @store_extractelt_v2i64(ptr %x, ptr %p) nounwind {
589577
; RV64: # %bb.0:
590578
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
591579
; RV64-NEXT: vle64.v v8, (a0)
592-
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
593580
; RV64-NEXT: vslidedown.vi v8, v8, 1
581+
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
594582
; RV64-NEXT: vse64.v v8, (a1)
595583
; RV64-NEXT: ret
596584
%a = load <2 x i64>, ptr %x
@@ -604,8 +592,8 @@ define void @store_extractelt_v2f64(ptr %x, ptr %p) nounwind {
604592
; CHECK: # %bb.0:
605593
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
606594
; CHECK-NEXT: vle64.v v8, (a0)
607-
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
608595
; CHECK-NEXT: vslidedown.vi v8, v8, 1
596+
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
609597
; CHECK-NEXT: vse64.v v8, (a1)
610598
; CHECK-NEXT: ret
611599
%a = load <2 x double>, ptr %x
@@ -627,7 +615,6 @@ define i32 @extractelt_add_v4i32(<4 x i32> %x) {
627615
; RV64: # %bb.0:
628616
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
629617
; RV64-NEXT: vadd.vi v8, v8, 13
630-
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
631618
; RV64-NEXT: vslidedown.vi v8, v8, 2
632619
; RV64-NEXT: vmv.x.s a0, v8
633620
; RV64-NEXT: ret
@@ -650,7 +637,6 @@ define i32 @extractelt_sub_v4i32(<4 x i32> %x) {
650637
; RV64: # %bb.0:
651638
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
652639
; RV64-NEXT: vrsub.vi v8, v8, 13
653-
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
654640
; RV64-NEXT: vslidedown.vi v8, v8, 2
655641
; RV64-NEXT: vmv.x.s a0, v8
656642
; RV64-NEXT: ret
@@ -665,7 +651,6 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
665651
; RV32NOM-NEXT: li a0, 13
666652
; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma
667653
; RV32NOM-NEXT: vmul.vx v8, v8, a0
668-
; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
669654
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
670655
; RV32NOM-NEXT: vmv.x.s a0, v8
671656
; RV32NOM-NEXT: ret
@@ -684,7 +669,6 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
684669
; RV64-NEXT: li a0, 13
685670
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
686671
; RV64-NEXT: vmul.vx v8, v8, a0
687-
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
688672
; RV64-NEXT: vslidedown.vi v8, v8, 2
689673
; RV64-NEXT: vmv.x.s a0, v8
690674
; RV64-NEXT: ret
@@ -712,7 +696,6 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
712696
; RV32NOM-NEXT: vsra.vv v9, v8, v11
713697
; RV32NOM-NEXT: vsrl.vi v8, v8, 31
714698
; RV32NOM-NEXT: vadd.vv v8, v9, v8
715-
; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
716699
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
717700
; RV32NOM-NEXT: vmv.x.s a0, v8
718701
; RV32NOM-NEXT: ret
@@ -748,7 +731,6 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
748731
; RV64-NEXT: vsra.vv v8, v8, v11
749732
; RV64-NEXT: vsrl.vi v9, v8, 31
750733
; RV64-NEXT: vadd.vv v8, v8, v9
751-
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
752734
; RV64-NEXT: vslidedown.vi v8, v8, 2
753735
; RV64-NEXT: vmv.x.s a0, v8
754736
; RV64-NEXT: ret
@@ -765,7 +747,6 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
765747
; RV32NOM-NEXT: lui a0, 322639
766748
; RV32NOM-NEXT: addi a0, a0, -945
767749
; RV32NOM-NEXT: vmulhu.vx v8, v8, a0
768-
; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
769750
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
770751
; RV32NOM-NEXT: vmv.x.s a0, v8
771752
; RV32NOM-NEXT: srli a0, a0, 2
@@ -790,7 +771,6 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
790771
; RV64-NEXT: addiw a0, a0, -945
791772
; RV64-NEXT: vmulhu.vx v8, v8, a0
792773
; RV64-NEXT: vsrl.vi v8, v8, 2
793-
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
794774
; RV64-NEXT: vslidedown.vi v8, v8, 2
795775
; RV64-NEXT: vmv.x.s a0, v8
796776
; RV64-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -776,9 +776,9 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
776776
; LMULMAX1-RV32-NEXT: vle16.v v9, (a0)
777777
; LMULMAX1-RV32-NEXT: vfncvt.f.f.w v10, v8
778778
; LMULMAX1-RV32-NEXT: vfsgnjn.vv v8, v9, v10
779-
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
780779
; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
781780
; LMULMAX1-RV32-NEXT: addi a1, a0, 4
781+
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
782782
; LMULMAX1-RV32-NEXT: vse16.v v9, (a1)
783783
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
784784
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
@@ -792,9 +792,9 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
792792
; LMULMAX1-RV64-NEXT: vle32.v v9, (a1)
793793
; LMULMAX1-RV64-NEXT: vfncvt.f.f.w v10, v9
794794
; LMULMAX1-RV64-NEXT: vfsgnjn.vv v8, v8, v10
795-
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
796795
; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
797796
; LMULMAX1-RV64-NEXT: addi a1, a0, 4
797+
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
798798
; LMULMAX1-RV64-NEXT: vse16.v v9, (a1)
799799
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
800800
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)

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