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Utilizing MCRegAliasIterator to check for all possible liveIn alias in SILowerSPGRSpills.
1 parent 6a7f07d commit 0268630

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4 files changed

+16
-51
lines changed

4 files changed

+16
-51
lines changed

‎llvm/include/llvm/CodeGen/MachineBasicBlock.h

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@
1313
#ifndef LLVM_CODEGEN_MACHINEBASICBLOCK_H
1414
#define LLVM_CODEGEN_MACHINEBASICBLOCK_H
1515

16-
#include "llvm/ADT/BitVector.h"
1716
#include "llvm/ADT/DenseMapInfo.h"
1817
#include "llvm/ADT/GraphTraits.h"
1918
#include "llvm/ADT/SparseBitVector.h"
@@ -159,7 +158,6 @@ class MachineBasicBlock
159158

160159
MachineFunction *xParent;
161160
Instructions Insts;
162-
const TargetRegisterInfo *TRI;
163161

164162
/// Keep track of the predecessor / successor basic blocks.
165163
SmallVector<MachineBasicBlock *, 4> Predecessors;
@@ -179,10 +177,6 @@ class MachineBasicBlock
179177
using LiveInVector = std::vector<RegisterMaskPair>;
180178
LiveInVector LiveIns;
181179

182-
/// Keeps track of live register units for those physical registers which
183-
/// are livein of the basicblock.
184-
BitVector LiveInRegUnits;
185-
186180
/// Alignment of the basic block. One if the basic block does not need to be
187181
/// aligned.
188182
Align Alignment;
@@ -464,17 +458,11 @@ class MachineBasicBlock
464458
void addLiveIn(MCRegister PhysReg,
465459
LaneBitmask LaneMask = LaneBitmask::getAll()) {
466460
LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
467-
addLiveInRegUnit(PhysReg, LaneMask);
468461
}
469462
void addLiveIn(const RegisterMaskPair &RegMaskPair) {
470463
LiveIns.push_back(RegMaskPair);
471-
addLiveInRegUnit(RegMaskPair.PhysReg, RegMaskPair.LaneMask);
472464
}
473465

474-
// Sets the register units for Reg based on the LaneMask in the
475-
// LiveInRegUnits.
476-
void addLiveInRegUnit(MCRegister Reg, LaneBitmask LaneMask);
477-
478466
/// Sorts and uniques the LiveIns vector. It can be significantly faster to do
479467
/// this than repeatedly calling isLiveIn before calling addLiveIn for every
480468
/// LiveIn insertion.
@@ -496,9 +484,6 @@ class MachineBasicBlock
496484
void removeLiveIn(MCRegister Reg,
497485
LaneBitmask LaneMask = LaneBitmask::getAll());
498486

499-
/// Resets the register units from LiveInRegUnits for the specified regsiters.
500-
void removeLiveInRegUnit(MCRegister Reg);
501-
502487
/// Return true if the specified register is in the live in set.
503488
bool isLiveIn(MCRegister Reg,
504489
LaneBitmask LaneMask = LaneBitmask::getAll()) const;

‎llvm/lib/CodeGen/MachineBasicBlock.cpp

Lines changed: 5 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,6 @@
3535
#include "llvm/IR/ModuleSlotTracker.h"
3636
#include "llvm/MC/MCAsmInfo.h"
3737
#include "llvm/MC/MCContext.h"
38-
#include "llvm/MC/MCRegisterInfo.h"
3938
#include "llvm/Support/Debug.h"
4039
#include "llvm/Support/raw_ostream.h"
4140
#include "llvm/Target/TargetMachine.h"
@@ -52,12 +51,10 @@ static cl::opt<bool> PrintSlotIndexes(
5251
cl::init(true), cl::Hidden);
5352

5453
MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
55-
: BB(B), Number(-1), xParent(&MF),
56-
TRI(MF.getSubtarget().getRegisterInfo()) {
54+
: BB(B), Number(-1), xParent(&MF) {
5755
Insts.Parent = this;
5856
if (B)
5957
IrrLoopHeaderWeight = B->getIrrLoopHeaderWeight();
60-
LiveInRegUnits.resize(TRI->getNumRegUnits());
6158
}
6259

6360
MachineBasicBlock::~MachineBasicBlock() = default;
@@ -600,47 +597,28 @@ void MachineBasicBlock::printAsOperand(raw_ostream &OS,
600597
printName(OS, 0);
601598
}
602599

603-
void MachineBasicBlock::addLiveInRegUnit(MCRegister Reg, LaneBitmask LaneMask) {
604-
for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
605-
LaneBitmask UnitMask = (*Unit).second;
606-
if ((UnitMask & LaneMask).any())
607-
LiveInRegUnits.set((*Unit).first);
608-
}
609-
}
610-
611600
void MachineBasicBlock::removeLiveIn(MCRegister Reg, LaneBitmask LaneMask) {
612601
LiveInVector::iterator I = find_if(
613602
LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
614603
if (I == LiveIns.end())
615604
return;
616605

617606
I->LaneMask &= ~LaneMask;
618-
if (I->LaneMask.none()) {
607+
if (I->LaneMask.none())
619608
LiveIns.erase(I);
620-
removeLiveInRegUnit(I->PhysReg);
621-
}
622609
}
623610

624611
MachineBasicBlock::livein_iterator
625612
MachineBasicBlock::removeLiveIn(MachineBasicBlock::livein_iterator I) {
626613
// Get non-const version of iterator.
627614
LiveInVector::iterator LI = LiveIns.begin() + (I - LiveIns.begin());
628-
removeLiveInRegUnit(LI->PhysReg);
629615
return LiveIns.erase(LI);
630616
}
631617

632-
void MachineBasicBlock::removeLiveInRegUnit(MCRegister Reg) {
633-
for (MCRegUnit Unit : TRI->regunits(Reg))
634-
LiveInRegUnits.reset(Unit);
635-
}
636-
637618
bool MachineBasicBlock::isLiveIn(MCRegister Reg, LaneBitmask LaneMask) const {
638-
for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
639-
LaneBitmask UnitMask = (*Unit).second;
640-
if ((UnitMask & LaneMask).any() && LiveInRegUnits.test((*Unit).first))
641-
return true;
642-
}
643-
return false;
619+
livein_iterator I = find_if(
620+
LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
621+
return I != livein_end() && (I->LaneMask & LaneMask).any();
644622
}
645623

646624
void MachineBasicBlock::sortUniqueLiveIns() {
@@ -1773,14 +1751,12 @@ MachineBasicBlock::getEndClobberMask(const TargetRegisterInfo *TRI) const {
17731751

17741752
void MachineBasicBlock::clearLiveIns() {
17751753
LiveIns.clear();
1776-
LiveInRegUnits.reset();
17771754
}
17781755

17791756
void MachineBasicBlock::clearLiveIns(
17801757
std::vector<RegisterMaskPair> &OldLiveIns) {
17811758
assert(OldLiveIns.empty() && "Vector must be empty");
17821759
std::swap(LiveIns, OldLiveIns);
1783-
LiveInRegUnits.reset();
17841760
}
17851761

17861762
MachineBasicBlock::livein_iterator MachineBasicBlock::livein_begin() const {

‎llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -114,8 +114,6 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
114114

115115
MachineBasicBlock::iterator I = SaveBlock.begin();
116116
if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
117-
const MachineRegisterInfo &MRI = MF.getRegInfo();
118-
119117
for (const CalleeSavedInfo &CS : CSI) {
120118
// Insert the spill to the stack frame.
121119
MCRegister Reg = CS.getReg();
@@ -128,7 +126,13 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
128126
// incoming register value, so don't kill at the spill point. This happens
129127
// since we pass some special inputs (workgroup IDs) in the callee saved
130128
// range.
131-
const bool IsLiveIn = SaveBlock.isLiveIn(Reg);
129+
bool IsLiveIn = false;
130+
for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) {
131+
if (SaveBlock.isLiveIn(*R)) {
132+
IsLiveIn = true;
133+
break;
134+
}
135+
}
132136
TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(),
133137
RC, TRI, Register());
134138

‎llvm/test/CodeGen/ARM/aes-erratum-fix.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,8 @@ define arm_aapcs_vfpcc void @aese_via_call2(half %0, ptr %1) nounwind {
6868
; CHECK-FIX-NEXT: push {r4, lr}
6969
; CHECK-FIX-NEXT: mov r4, r0
7070
; CHECK-FIX-NEXT: bl get_inputf16
71-
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
7271
; CHECK-FIX-NEXT: vorr q0, q0, q0
72+
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
7373
; CHECK-FIX-NEXT: aese.8 q8, q0
7474
; CHECK-FIX-NEXT: aesmc.8 q8, q8
7575
; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4]
@@ -89,8 +89,8 @@ define arm_aapcs_vfpcc void @aese_via_call3(float %0, ptr %1) nounwind {
8989
; CHECK-FIX-NEXT: push {r4, lr}
9090
; CHECK-FIX-NEXT: mov r4, r0
9191
; CHECK-FIX-NEXT: bl get_inputf32
92-
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
9392
; CHECK-FIX-NEXT: vorr q0, q0, q0
93+
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
9494
; CHECK-FIX-NEXT: aese.8 q8, q0
9595
; CHECK-FIX-NEXT: aesmc.8 q8, q8
9696
; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4]
@@ -2222,8 +2222,8 @@ define arm_aapcs_vfpcc void @aesd_via_call2(half %0, ptr %1) nounwind {
22222222
; CHECK-FIX-NEXT: push {r4, lr}
22232223
; CHECK-FIX-NEXT: mov r4, r0
22242224
; CHECK-FIX-NEXT: bl get_inputf16
2225-
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
22262225
; CHECK-FIX-NEXT: vorr q0, q0, q0
2226+
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
22272227
; CHECK-FIX-NEXT: aesd.8 q8, q0
22282228
; CHECK-FIX-NEXT: aesimc.8 q8, q8
22292229
; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4]
@@ -2243,8 +2243,8 @@ define arm_aapcs_vfpcc void @aesd_via_call3(float %0, ptr %1) nounwind {
22432243
; CHECK-FIX-NEXT: push {r4, lr}
22442244
; CHECK-FIX-NEXT: mov r4, r0
22452245
; CHECK-FIX-NEXT: bl get_inputf32
2246-
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
22472246
; CHECK-FIX-NEXT: vorr q0, q0, q0
2247+
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
22482248
; CHECK-FIX-NEXT: aesd.8 q8, q0
22492249
; CHECK-FIX-NEXT: aesimc.8 q8, q8
22502250
; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4]

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