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michaelmaitlandmichaelmaitland
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fixup! better test coverage of idx argument
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+65
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‎llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll

Lines changed: 65 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -48,31 +48,32 @@ define <vscale x 1 x i1> @insertelement_nxv1i1_1() {
4848
ret <vscale x 1 x i1> %a
4949
}
5050

51-
define <vscale x 1 x i1> @insertelement_nxv1i1_2(i1 %x) {
51+
define <vscale x 1 x i1> @insertelement_nxv1i1_2(i1 %x, i32 %idx) {
5252
; RV32-LABEL: name: insertelement_nxv1i1_2
5353
; RV32: bb.1 (%ir-block.0):
54-
; RV32-NEXT: liveins: $x10
54+
; RV32-NEXT: liveins: $x10, $x11
5555
; RV32-NEXT: {{ $}}
5656
; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
5757
; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
58+
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
5859
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
59-
; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
60-
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)
60+
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)
6161
; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>)
6262
; RV32-NEXT: PseudoRET implicit $v0
6363
;
6464
; RV64-LABEL: name: insertelement_nxv1i1_2
6565
; RV64: bb.1 (%ir-block.0):
66-
; RV64-NEXT: liveins: $x10
66+
; RV64-NEXT: liveins: $x10, $x11
6767
; RV64-NEXT: {{ $}}
6868
; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
6969
; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
70+
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
71+
; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
7072
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
71-
; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
72-
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)
73+
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32)
7374
; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>)
7475
; RV64-NEXT: PseudoRET implicit $v0
75-
%a = insertelement <vscale x 1 x i1> poison, i1 %x, i32 0
76+
%a = insertelement <vscale x 1 x i1> poison, i1 %x, i32 %idx
7677
ret <vscale x 1 x i1> %a
7778
}
7879

@@ -81,7 +82,7 @@ define <vscale x 2 x i1> @insertelement_nxv2i1_0() {
8182
; RV32: bb.1 (%ir-block.0):
8283
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
8384
; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
84-
; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
85+
; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
8586
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)
8687
; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
8788
; RV32-NEXT: PseudoRET implicit $v0
@@ -90,11 +91,11 @@ define <vscale x 2 x i1> @insertelement_nxv2i1_0() {
9091
; RV64: bb.1 (%ir-block.0):
9192
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
9293
; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
93-
; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
94+
; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
9495
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)
9596
; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
9697
; RV64-NEXT: PseudoRET implicit $v0
97-
%a = insertelement <vscale x 2 x i1> poison, i1 0, i32 0
98+
%a = insertelement <vscale x 2 x i1> poison, i1 0, i32 1
9899
ret <vscale x 2 x i1> %a
99100
}
100101

@@ -120,31 +121,32 @@ define <vscale x 2 x i1> @insertelement_nxv2i1_1() {
120121
ret <vscale x 2 x i1> %a
121122
}
122123

123-
define <vscale x 2 x i1> @insertelement_nxv2i1_2(i1 %x) {
124+
define <vscale x 2 x i1> @insertelement_nxv2i1_2(i1 %x, i32 %idx) {
124125
; RV32-LABEL: name: insertelement_nxv2i1_2
125126
; RV32: bb.1 (%ir-block.0):
126-
; RV32-NEXT: liveins: $x10
127+
; RV32-NEXT: liveins: $x10, $x11
127128
; RV32-NEXT: {{ $}}
128129
; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
129130
; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
131+
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
130132
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
131-
; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
132-
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)
133+
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)
133134
; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
134135
; RV32-NEXT: PseudoRET implicit $v0
135136
;
136137
; RV64-LABEL: name: insertelement_nxv2i1_2
137138
; RV64: bb.1 (%ir-block.0):
138-
; RV64-NEXT: liveins: $x10
139+
; RV64-NEXT: liveins: $x10, $x11
139140
; RV64-NEXT: {{ $}}
140141
; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
141142
; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
143+
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
144+
; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
142145
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
143-
; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
144-
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)
146+
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32)
145147
; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
146148
; RV64-NEXT: PseudoRET implicit $v0
147-
%a = insertelement <vscale x 2 x i1> poison, i1 %x, i32 0
149+
%a = insertelement <vscale x 2 x i1> poison, i1 %x, i32 %idx
148150
ret <vscale x 2 x i1> %a
149151
}
150152

@@ -153,7 +155,7 @@ define <vscale x 4 x i1> @insertelement_nxv4i1_0() {
153155
; RV32: bb.1 (%ir-block.0):
154156
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
155157
; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
156-
; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
158+
; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
157159
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)
158160
; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
159161
; RV32-NEXT: PseudoRET implicit $v0
@@ -162,11 +164,11 @@ define <vscale x 4 x i1> @insertelement_nxv4i1_0() {
162164
; RV64: bb.1 (%ir-block.0):
163165
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
164166
; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
165-
; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
167+
; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
166168
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)
167169
; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
168170
; RV64-NEXT: PseudoRET implicit $v0
169-
%a = insertelement <vscale x 4 x i1> poison, i1 0, i32 0
171+
%a = insertelement <vscale x 4 x i1> poison, i1 0, i32 2
170172
ret <vscale x 4 x i1> %a
171173
}
172174

@@ -264,31 +266,32 @@ define <vscale x 8 x i1> @insertelement_nxv8i1_1() {
264266
ret <vscale x 8 x i1> %a
265267
}
266268

267-
define <vscale x 8 x i1> @insertelement_nxv8i1_2(i1 %x) {
269+
define <vscale x 8 x i1> @insertelement_nxv8i1_2(i1 %x, i32 %idx) {
268270
; RV32-LABEL: name: insertelement_nxv8i1_2
269271
; RV32: bb.1 (%ir-block.0):
270-
; RV32-NEXT: liveins: $x10
272+
; RV32-NEXT: liveins: $x10, $x11
271273
; RV32-NEXT: {{ $}}
272274
; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
273275
; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
276+
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
274277
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
275-
; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
276-
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)
278+
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)
277279
; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>)
278280
; RV32-NEXT: PseudoRET implicit $v0
279281
;
280282
; RV64-LABEL: name: insertelement_nxv8i1_2
281283
; RV64: bb.1 (%ir-block.0):
282-
; RV64-NEXT: liveins: $x10
284+
; RV64-NEXT: liveins: $x10, $x11
283285
; RV64-NEXT: {{ $}}
284286
; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
285287
; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
288+
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
289+
; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
286290
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
287-
; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
288-
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)
291+
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32)
289292
; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>)
290293
; RV64-NEXT: PseudoRET implicit $v0
291-
%a = insertelement <vscale x 8 x i1> poison, i1 %x, i32 0
294+
%a = insertelement <vscale x 8 x i1> poison, i1 %x, i32 %idx
292295
ret <vscale x 8 x i1> %a
293296
}
294297

@@ -297,7 +300,7 @@ define <vscale x 16 x i1> @insertelement_nxv16i1_0() {
297300
; RV32: bb.1 (%ir-block.0):
298301
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
299302
; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
300-
; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
303+
; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
301304
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)
302305
; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
303306
; RV32-NEXT: PseudoRET implicit $v0
@@ -306,11 +309,11 @@ define <vscale x 16 x i1> @insertelement_nxv16i1_0() {
306309
; RV64: bb.1 (%ir-block.0):
307310
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
308311
; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
309-
; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
312+
; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
310313
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)
311314
; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
312315
; RV64-NEXT: PseudoRET implicit $v0
313-
%a = insertelement <vscale x 16 x i1> poison, i1 0, i32 0
316+
%a = insertelement <vscale x 16 x i1> poison, i1 0, i32 15
314317
ret <vscale x 16 x i1> %a
315318
}
316319

@@ -336,31 +339,32 @@ define <vscale x 16 x i1> @insertelement_nxv16i1_1() {
336339
ret <vscale x 16 x i1> %a
337340
}
338341

339-
define <vscale x 16 x i1> @insertelement_nxv16i1_2(i1 %x) {
342+
define <vscale x 16 x i1> @insertelement_nxv16i1_2(i1 %x, i32 %idx) {
340343
; RV32-LABEL: name: insertelement_nxv16i1_2
341344
; RV32: bb.1 (%ir-block.0):
342-
; RV32-NEXT: liveins: $x10
345+
; RV32-NEXT: liveins: $x10, $x11
343346
; RV32-NEXT: {{ $}}
344347
; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
345348
; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
349+
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
346350
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
347-
; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
348-
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)
351+
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)
349352
; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
350353
; RV32-NEXT: PseudoRET implicit $v0
351354
;
352355
; RV64-LABEL: name: insertelement_nxv16i1_2
353356
; RV64: bb.1 (%ir-block.0):
354-
; RV64-NEXT: liveins: $x10
357+
; RV64-NEXT: liveins: $x10, $x11
355358
; RV64-NEXT: {{ $}}
356359
; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
357360
; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
361+
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
362+
; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
358363
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
359-
; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
360-
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)
364+
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32)
361365
; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
362366
; RV64-NEXT: PseudoRET implicit $v0
363-
%a = insertelement <vscale x 16 x i1> poison, i1 %x, i32 0
367+
%a = insertelement <vscale x 16 x i1> poison, i1 %x, i32 %idx
364368
ret <vscale x 16 x i1> %a
365369
}
366370

@@ -685,20 +689,20 @@ define <vscale x 16 x i8> @insertelement_nxv16i8_0() {
685689
; RV32: bb.1 (%ir-block.0):
686690
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
687691
; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
688-
; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
689-
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)
692+
; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
693+
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)
690694
; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
691695
; RV32-NEXT: PseudoRET implicit $v8m2
692696
;
693697
; RV64-LABEL: name: insertelement_nxv16i8_0
694698
; RV64: bb.1 (%ir-block.0):
695699
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
696700
; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
697-
; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
698-
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)
701+
; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
702+
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)
699703
; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
700704
; RV64-NEXT: PseudoRET implicit $v8m2
701-
%a = insertelement <vscale x 16 x i8> poison, i8 0, i32 0
705+
%a = insertelement <vscale x 16 x i8> poison, i8 0, i64 0
702706
ret <vscale x 16 x i8> %a
703707
}
704708

@@ -724,31 +728,33 @@ define <vscale x 16 x i8> @insertelement_nxv16i8_1() {
724728
ret <vscale x 16 x i8> %a
725729
}
726730

727-
define <vscale x 16 x i8> @insertelement_nxv16i8_2(i8 %x) {
731+
define <vscale x 16 x i8> @insertelement_nxv16i8_2(i8 %x, i64 %idx) {
728732
; RV32-LABEL: name: insertelement_nxv16i8_2
729733
; RV32: bb.1 (%ir-block.0):
730-
; RV32-NEXT: liveins: $x10
734+
; RV32-NEXT: liveins: $x10, $x11, $x12
731735
; RV32-NEXT: {{ $}}
732736
; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
733737
; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
738+
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
739+
; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
740+
; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
734741
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
735-
; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
736-
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)
742+
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[MV]](s64)
737743
; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
738744
; RV32-NEXT: PseudoRET implicit $v8m2
739745
;
740746
; RV64-LABEL: name: insertelement_nxv16i8_2
741747
; RV64: bb.1 (%ir-block.0):
742-
; RV64-NEXT: liveins: $x10
748+
; RV64-NEXT: liveins: $x10, $x11
743749
; RV64-NEXT: {{ $}}
744750
; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
745751
; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
752+
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
746753
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
747-
; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
748-
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)
754+
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[COPY1]](s64)
749755
; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
750756
; RV64-NEXT: PseudoRET implicit $v8m2
751-
%a = insertelement <vscale x 16 x i8> poison, i8 %x, i32 0
757+
%a = insertelement <vscale x 16 x i8> poison, i8 %x, i64 %idx
752758
ret <vscale x 16 x i8> %a
753759
}
754760

@@ -857,20 +863,20 @@ define <vscale x 2 x i16> @insertelement_nxv2i16_0() {
857863
; RV32: bb.1 (%ir-block.0):
858864
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
859865
; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
860-
; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
861-
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)
866+
; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
867+
; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)
862868
; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>)
863869
; RV32-NEXT: PseudoRET implicit $v8
864870
;
865871
; RV64-LABEL: name: insertelement_nxv2i16_0
866872
; RV64: bb.1 (%ir-block.0):
867873
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
868874
; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
869-
; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
870-
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)
875+
; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
876+
; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)
871877
; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>)
872878
; RV64-NEXT: PseudoRET implicit $v8
873-
%a = insertelement <vscale x 2 x i16> poison, i16 0, i32 0
879+
%a = insertelement <vscale x 2 x i16> poison, i16 0, i64 1
874880
ret <vscale x 2 x i16> %a
875881
}
876882

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