@@ -429,63 +429,47 @@ bool SIFoldOperands::tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
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if (isUseMIInFoldList (FoldList, MI))
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return false ;
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- unsigned CommuteOpNo = OpNo;
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-
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// Operand is not legal, so try to commute the instruction to
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// see if this makes it possible to fold.
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- unsigned CommuteIdx0 = TargetInstrInfo::CommuteAnyOperandIndex;
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- unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;
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- bool CanCommute = TII->findCommutedOpIndices (*MI, CommuteIdx0, CommuteIdx1);
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-
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- if (CanCommute) {
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- if (CommuteIdx0 == OpNo)
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- CommuteOpNo = CommuteIdx1;
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- else if (CommuteIdx1 == OpNo)
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- CommuteOpNo = CommuteIdx0;
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- }
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-
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+ unsigned CommuteOpNo = TargetInstrInfo::CommuteAnyOperandIndex;
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+ bool CanCommute = TII->findCommutedOpIndices (*MI, OpNo, CommuteOpNo);
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+ if (!CanCommute)
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+ return false ;
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// One of operands might be an Imm operand, and OpNo may refer to it after
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// the call of commuteInstruction() below. Such situations are avoided
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// here explicitly as OpNo must be a register operand to be a candidate
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// for memory folding.
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- if (CanCommute && (!MI->getOperand (CommuteIdx0).isReg () ||
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- !MI->getOperand (CommuteIdx1).isReg ()))
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+ if (!MI->getOperand (OpNo).isReg () || !MI->getOperand (CommuteOpNo).isReg ())
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return false ;
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- if (!CanCommute ||
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- !TII->commuteInstruction (*MI, false , CommuteIdx0, CommuteIdx1))
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+ if (!TII->commuteInstruction (*MI, false , OpNo, CommuteOpNo))
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return false ;
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+ int Op32 = -1 ;
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if (!TII->isOperandLegal (*MI, CommuteOpNo, OpToFold)) {
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- if ((Opc == AMDGPU::V_ADD_CO_U32_e64 ||
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- Opc == AMDGPU::V_SUB_CO_U32_e64 ||
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- Opc == AMDGPU::V_SUBREV_CO_U32_e64) && // FIXME
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- (OpToFold->isImm () || OpToFold->isFI () || OpToFold->isGlobal ())) {
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-
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- // Verify the other operand is a VGPR, otherwise we would violate the
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- // constant bus restriction.
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- unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0;
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- MachineOperand &OtherOp = MI->getOperand (OtherIdx);
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- if (!OtherOp.isReg () ||
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- !TII->getRegisterInfo ().isVGPR (*MRI, OtherOp.getReg ()))
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- return false ;
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-
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- assert (MI->getOperand (1 ).isDef ());
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+ if ((Opc != AMDGPU::V_ADD_CO_U32_e64 && Opc != AMDGPU::V_SUB_CO_U32_e64 &&
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+ Opc != AMDGPU::V_SUBREV_CO_U32_e64) || // FIXME
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+ (!OpToFold->isImm () && !OpToFold->isFI () && !OpToFold->isGlobal ())) {
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+ TII->commuteInstruction (*MI, false , OpNo, CommuteOpNo);
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+ return false ;
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+ }
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- // Make sure to get the 32-bit version of the commuted opcode.
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- unsigned MaybeCommutedOpc = MI->getOpcode ();
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- int Op32 = AMDGPU::getVOPe32 (MaybeCommutedOpc);
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+ // Verify the other operand is a VGPR, otherwise we would violate the
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+ // constant bus restriction.
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+ MachineOperand &OtherOp = MI->getOperand (OpNo);
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+ if (!OtherOp.isReg () ||
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+ !TII->getRegisterInfo ().isVGPR (*MRI, OtherOp.getReg ()))
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+ return false ;
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- appendFoldCandidate (FoldList, MI, CommuteOpNo, OpToFold, true , Op32);
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- return true ;
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- }
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+ assert (MI->getOperand (1 ).isDef ());
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- TII->commuteInstruction (*MI, false , CommuteIdx0, CommuteIdx1);
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- return false ;
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+ // Make sure to get the 32-bit version of the commuted opcode.
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+ unsigned MaybeCommutedOpc = MI->getOpcode ();
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+ Op32 = AMDGPU::getVOPe32 (MaybeCommutedOpc);
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}
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- appendFoldCandidate (FoldList, MI, CommuteOpNo, OpToFold, true );
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+ appendFoldCandidate (FoldList, MI, CommuteOpNo, OpToFold, true , Op32 );
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return true ;
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}
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