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[AMDGPU] Simplify commuted operand handling. NFCI. (#71965)
SIInstrInfo::commuteInstructionImpl should accept indices to commute in either order. This simplifies SIFoldOperands::tryAddToFoldList where OtherIdx, CommuteIdx0 and CommuteIdx1 are no longer needed.
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2 files changed

+27
-40
lines changed

2 files changed

+27
-40
lines changed

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Lines changed: 24 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -429,63 +429,47 @@ bool SIFoldOperands::tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
429429
if (isUseMIInFoldList(FoldList, MI))
430430
return false;
431431

432-
unsigned CommuteOpNo = OpNo;
433-
434432
// Operand is not legal, so try to commute the instruction to
435433
// see if this makes it possible to fold.
436-
unsigned CommuteIdx0 = TargetInstrInfo::CommuteAnyOperandIndex;
437-
unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;
438-
bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1);
439-
440-
if (CanCommute) {
441-
if (CommuteIdx0 == OpNo)
442-
CommuteOpNo = CommuteIdx1;
443-
else if (CommuteIdx1 == OpNo)
444-
CommuteOpNo = CommuteIdx0;
445-
}
446-
434+
unsigned CommuteOpNo = TargetInstrInfo::CommuteAnyOperandIndex;
435+
bool CanCommute = TII->findCommutedOpIndices(*MI, OpNo, CommuteOpNo);
436+
if (!CanCommute)
437+
return false;
447438

448439
// One of operands might be an Imm operand, and OpNo may refer to it after
449440
// the call of commuteInstruction() below. Such situations are avoided
450441
// here explicitly as OpNo must be a register operand to be a candidate
451442
// for memory folding.
452-
if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
453-
!MI->getOperand(CommuteIdx1).isReg()))
443+
if (!MI->getOperand(OpNo).isReg() || !MI->getOperand(CommuteOpNo).isReg())
454444
return false;
455445

456-
if (!CanCommute ||
457-
!TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1))
446+
if (!TII->commuteInstruction(*MI, false, OpNo, CommuteOpNo))
458447
return false;
459448

449+
int Op32 = -1;
460450
if (!TII->isOperandLegal(*MI, CommuteOpNo, OpToFold)) {
461-
if ((Opc == AMDGPU::V_ADD_CO_U32_e64 ||
462-
Opc == AMDGPU::V_SUB_CO_U32_e64 ||
463-
Opc == AMDGPU::V_SUBREV_CO_U32_e64) && // FIXME
464-
(OpToFold->isImm() || OpToFold->isFI() || OpToFold->isGlobal())) {
465-
466-
// Verify the other operand is a VGPR, otherwise we would violate the
467-
// constant bus restriction.
468-
unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0;
469-
MachineOperand &OtherOp = MI->getOperand(OtherIdx);
470-
if (!OtherOp.isReg() ||
471-
!TII->getRegisterInfo().isVGPR(*MRI, OtherOp.getReg()))
472-
return false;
473-
474-
assert(MI->getOperand(1).isDef());
451+
if ((Opc != AMDGPU::V_ADD_CO_U32_e64 && Opc != AMDGPU::V_SUB_CO_U32_e64 &&
452+
Opc != AMDGPU::V_SUBREV_CO_U32_e64) || // FIXME
453+
(!OpToFold->isImm() && !OpToFold->isFI() && !OpToFold->isGlobal())) {
454+
TII->commuteInstruction(*MI, false, OpNo, CommuteOpNo);
455+
return false;
456+
}
475457

476-
// Make sure to get the 32-bit version of the commuted opcode.
477-
unsigned MaybeCommutedOpc = MI->getOpcode();
478-
int Op32 = AMDGPU::getVOPe32(MaybeCommutedOpc);
458+
// Verify the other operand is a VGPR, otherwise we would violate the
459+
// constant bus restriction.
460+
MachineOperand &OtherOp = MI->getOperand(OpNo);
461+
if (!OtherOp.isReg() ||
462+
!TII->getRegisterInfo().isVGPR(*MRI, OtherOp.getReg()))
463+
return false;
479464

480-
appendFoldCandidate(FoldList, MI, CommuteOpNo, OpToFold, true, Op32);
481-
return true;
482-
}
465+
assert(MI->getOperand(1).isDef());
483466

484-
TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1);
485-
return false;
467+
// Make sure to get the 32-bit version of the commuted opcode.
468+
unsigned MaybeCommutedOpc = MI->getOpcode();
469+
Op32 = AMDGPU::getVOPe32(MaybeCommutedOpc);
486470
}
487471

488-
appendFoldCandidate(FoldList, MI, CommuteOpNo, OpToFold, true);
472+
appendFoldCandidate(FoldList, MI, CommuteOpNo, OpToFold, true, Op32);
489473
return true;
490474
}
491475

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2692,6 +2692,9 @@ MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
26922692
if (CommutedOpcode == -1)
26932693
return nullptr;
26942694

2695+
if (Src0Idx > Src1Idx)
2696+
std::swap(Src0Idx, Src1Idx);
2697+
26952698
assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) ==
26962699
static_cast<int>(Src0Idx) &&
26972700
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) ==

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