[X86] Only fold to v16i32 VPDPWSSD on targets with useAVX512Regs enabled.

Fixes #119158

Author: RKSimon

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -56911,7 +56911,7 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
 
   // Peephole for 512-bit VPDPBSSD on non-VLX targets.
   // TODO: Should this be part of matchPMADDWD/matchPMADDWD_2?
-  if (Subtarget.hasVNNI() && VT == MVT::v16i32) {
+  if (Subtarget.hasVNNI() && Subtarget.useAVX512Regs() && VT == MVT::v16i32) {
     using namespace SDPatternMatch;
     SDValue Accum, Lo0, Lo1, Hi0, Hi1;
     if (sd_match(N, m_Add(m_Value(Accum),

llvm/test/CodeGen/X86/pr119158.ll

@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+
+define dso_local void @foo() #1 {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %newFuncRoot
+; CHECK-NEXT:    vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
+; CHECK-NEXT:    vpbroadcastd {{.*#+}} ymm1 = [64,64,64,64,64,64,64,64]
+; CHECK-NEXT:    vpdpwssd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm1
+; CHECK-NEXT:    vpsrld $7, %ymm1, %ymm0
+; CHECK-NEXT:    vpackusdw %ymm0, %ymm0, %ymm0
+; CHECK-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
+; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+newFuncRoot:
+  br label %loop
+
+loop:                                              ; preds = %newFuncRoot, %loop
+  %0 = load <16 x i8>, ptr poison, align 1
+  %1 = zext <16 x i8> %0 to <16 x i32>
+  %2 = mul nuw nsw <16 x i32> %1, splat (i32 18)
+  %3 = add nuw nsw <16 x i32> zeroinitializer, splat (i32 64)
+  %4 = add nuw nsw <16 x i32> %3, zeroinitializer
+  %5 = add nuw nsw <16 x i32> %4, %2
+  %6 = sub nsw <16 x i32> %5, zeroinitializer
+  %7 = ashr <16 x i32> %6, splat (i32 7)
+  %8 = tail call <16 x i32> @llvm.smin.v16i32(<16 x i32> %7, <16 x i32> splat (i32 255))
+  %9 = tail call <16 x i32> @llvm.smax.v16i32(<16 x i32> %8, <16 x i32> zeroinitializer)
+  %10 = trunc <16 x i32> %9 to <16 x i8>
+  %11 = shufflevector <16 x i8> %10, <16 x i8> poison, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+  store <32 x i8> %11, ptr poison, align 1
+  br i1 poison, label %.exitStub, label %loop
+
+.exitStub:                                        ; preds = %loop
+  ret void
+}
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { "min-legal-vector-width"="0" "target-cpu"="tigerlake" "target-features"="+adx,+aes,+avx,+avx2,+avx512bitalg,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512ifma,+avx512vbmi,+avx512vbmi2,+avx512vl,+avx512vnni,+avx512vp2intersect,+avx512vpopcntdq,+bmi,+bmi2,+clflushopt,+clwb,+cmov,+crc32,+cx16,+cx8,+evex512,+f16c,+fma,+fsgsbase,+fxsr,+gfni,+invpcid,+kl,+lzcnt,+mmx,+movbe,+movdir64b,+movdiri,+pclmul,+pku,+popcnt,+prfchw,+rdpid,+rdrnd,+rdseed,+sahf,+sgx,+sha,+shstk,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+vaes,+vpclmulqdq,+widekl,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" }