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Pierre-vhPierre-vh
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[TableGen] Use buildConstant to emit apply pattern immediates (#66077)
Use `MachineIRBuilder::buildConstant` to emit typed immediates in 'apply' MIR patterns. This adds flexibility, e.g. it allows us to seamlessly handle vector cases, where a `G_BUILD_VECTOR` is needed to create a splat.
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-86
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10 files changed

+101
-86
lines changed

‎llvm/docs/GlobalISel/MIRPatterns.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -257,8 +257,8 @@ Common Pattern #3: Emitting a Constant Value
257257
When an immediate operand appears in an 'apply' pattern, the behavior
258258
depends on whether it's typed or not.
259259

260-
* If the immediate is typed, a ``G_CONSTANT`` is implicitly emitted
261-
(= a register operand is added to the instruction).
260+
* If the immediate is typed, ``MachineIRBuilder::buildConstant`` is used
261+
to create a ``G_CONSTANT``. A ``G_BUILD_VECTOR`` will be used for vectors.
262262
* If the immediate is untyped, a simple immediate is added
263263
(``MachineInstrBuilder::addImm``).
264264

‎llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -292,6 +292,11 @@ enum {
292292
/// - Opcode - The new opcode to use
293293
GIR_BuildMI,
294294

295+
/// Builds a constant and stores its result in a TempReg.
296+
/// - TempRegID - Temp Register to define.
297+
/// - Imm - The immediate to add
298+
GIR_BuildConstant,
299+
295300
/// Copy an operand to the specified instruction
296301
/// - NewInsnID - Instruction ID to modify
297302
/// - OldInsnID - Instruction ID to copy from

‎llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -933,6 +933,16 @@ bool GIMatchTableExecutor::executeMatchTable(
933933
break;
934934
}
935935

936+
case GIR_BuildConstant: {
937+
int64_t TempRegID = MatchTable[CurrentIdx++];
938+
int64_t Imm = MatchTable[CurrentIdx++];
939+
Builder.buildConstant(State.TempRegisters[TempRegID], Imm);
940+
DEBUG_WITH_TYPE(TgtExecutor::getName(),
941+
dbgs() << CurrentIdx << ": GIR_BuildConstant(TempReg["
942+
<< TempRegID << "], Imm=" << Imm << ")\n");
943+
break;
944+
}
945+
936946
case GIR_Copy: {
937947
int64_t NewInsnID = MatchTable[CurrentIdx++];
938948
int64_t OldInsnID = MatchTable[CurrentIdx++];

‎llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
3434

3535
// CHECK: const int64_t *GenMyCombiner::getMatchTable() const {
3636
// CHECK-NEXT: constexpr static int64_t MatchTable0[] = {
37-
// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/19, 126, /*)*//*default:*//*Label 3*/ 202,
37+
// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/19, 126, /*)*//*default:*//*Label 3*/ 194,
3838
// CHECK-NEXT: /*TargetOpcode::COPY*//*Label 0*/ 112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3939
// CHECK-NEXT: /*TargetOpcode::G_CONSTANT*//*Label 1*/ 138, 0, 0, 0, 0, 0,
4040
// CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 2*/ 165,
@@ -69,25 +69,23 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
6969
// CHECK-NEXT: // Label 5: @164
7070
// CHECK-NEXT: GIM_Reject,
7171
// CHECK-NEXT: // Label 2: @165
72-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ 201, // Rule ID 1 //
72+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ 193, // Rule ID 1 //
7373
// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled,
7474
// CHECK-NEXT: // MIs[0] a
7575
// CHECK-NEXT: // No operand predicates
7676
// CHECK-NEXT: // MIs[0] Operand 1
7777
// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
7878
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
79-
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_CONSTANT,
80-
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
81-
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/1, /*Type*/GILLT_s32, /*Imm*/0,
79+
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
8280
// CHECK-NEXT: // Combiner Rule #1: InstTest1
8381
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8482
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a
8583
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8684
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
8785
// CHECK-NEXT: GIR_Done,
88-
// CHECK-NEXT: // Label 6: @201
86+
// CHECK-NEXT: // Label 6: @193
8987
// CHECK-NEXT: GIM_Reject,
90-
// CHECK-NEXT: // Label 3: @202
88+
// CHECK-NEXT: // Label 3: @194
9189
// CHECK-NEXT: GIM_Reject,
9290
// CHECK-NEXT: };
9391
// CHECK-NEXT: return MatchTable0;

‎llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td

Lines changed: 15 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -28,31 +28,29 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
2828

2929
// CHECK: const int64_t *GenMyCombiner::getMatchTable() const {
3030
// CHECK-NEXT: constexpr static int64_t MatchTable0[] = {
31-
// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/118, 181, /*)*//*default:*//*Label 3*/ 176,
31+
// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/118, 181, /*)*//*default:*//*Label 3*/ 152,
3232
// CHECK-NEXT: /*TargetOpcode::G_TRUNC*//*Label 0*/ 68, 0, 0, 0, 0, 0, 0,
33-
// CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 1*/ 101, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
34-
// CHECK-NEXT: /*TargetOpcode::G_FPEXT*//*Label 2*/ 143,
33+
// CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 1*/ 93, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
34+
// CHECK-NEXT: /*TargetOpcode::G_FPEXT*//*Label 2*/ 127,
3535
// CHECK-NEXT: // Label 0: @68
36-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ 100, // Rule ID 1 //
36+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ 92, // Rule ID 1 //
3737
// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
3838
// CHECK-NEXT: // MIs[0] root
3939
// CHECK-NEXT: // No operand predicates
4040
// CHECK-NEXT: // MIs[0] __Test0_match_0.z
4141
// CHECK-NEXT: // No operand predicates
4242
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43-
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_CONSTANT,
44-
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45-
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/1, /*Type*/GILLT_s32, /*Imm*/0,
43+
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
4644
// CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[1]]
4745
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4846
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root
4947
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5048
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
5149
// CHECK-NEXT: GIR_Done,
52-
// CHECK-NEXT: // Label 4: @100
50+
// CHECK-NEXT: // Label 4: @92
5351
// CHECK-NEXT: GIM_Reject,
54-
// CHECK-NEXT: // Label 1: @101
55-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ 142, // Rule ID 0 //
52+
// CHECK-NEXT: // Label 1: @93
53+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ 126, // Rule ID 0 //
5654
// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
5755
// CHECK-NEXT: // MIs[0] root
5856
// CHECK-NEXT: // No operand predicates
@@ -63,37 +61,33 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
6361
// CHECK-NEXT: // No operand predicates
6462
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
6563
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
66-
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_CONSTANT,
67-
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
68-
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/1, /*Type*/GILLT_s32, /*Imm*/0,
64+
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
6965
// CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[0]]
7066
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7167
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root
7268
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7369
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
7470
// CHECK-NEXT: GIR_Done,
75-
// CHECK-NEXT: // Label 5: @142
71+
// CHECK-NEXT: // Label 5: @126
7672
// CHECK-NEXT: GIM_Reject,
77-
// CHECK-NEXT: // Label 2: @143
78-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ 175, // Rule ID 2 //
73+
// CHECK-NEXT: // Label 2: @127
74+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ 151, // Rule ID 2 //
7975
// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
8076
// CHECK-NEXT: // MIs[0] root
8177
// CHECK-NEXT: // No operand predicates
8278
// CHECK-NEXT: // MIs[0] __Test0_match_0.z
8379
// CHECK-NEXT: // No operand predicates
8480
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
85-
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_CONSTANT,
86-
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
87-
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/1, /*Type*/GILLT_s32, /*Imm*/0,
81+
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
8882
// CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[2]]
8983
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9084
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root
9185
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9286
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
9387
// CHECK-NEXT: GIR_Done,
94-
// CHECK-NEXT: // Label 6: @175
88+
// CHECK-NEXT: // Label 6: @151
9589
// CHECK-NEXT: GIM_Reject,
96-
// CHECK-NEXT: // Label 3: @176
90+
// CHECK-NEXT: // Label 3: @152
9791
// CHECK-NEXT: GIM_Reject,
9892
// CHECK-NEXT: };
9993
// CHECK-NEXT: return MatchTable0;

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