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[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
1 parent 201da87 commit 0a4e1c5

8 files changed

+36
-40
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3194,11 +3194,17 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
31943194
case RISCV::SLLI_UW:
31953195
case RISCV::FMV_W_X:
31963196
case RISCV::FCVT_H_W:
3197+
case RISCV::FCVT_H_W_INX:
31973198
case RISCV::FCVT_H_WU:
3199+
case RISCV::FCVT_H_WU_INX:
31983200
case RISCV::FCVT_S_W:
3201+
case RISCV::FCVT_S_W_INX:
31993202
case RISCV::FCVT_S_WU:
3203+
case RISCV::FCVT_S_WU_INX:
32003204
case RISCV::FCVT_D_W:
3205+
case RISCV::FCVT_D_W_INX:
32013206
case RISCV::FCVT_D_WU:
3207+
case RISCV::FCVT_D_WU_INX:
32023208
case RISCV::TH_REVW:
32033209
case RISCV::TH_SRRIW:
32043210
if (Bits >= 32)

‎llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -174,11 +174,17 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
174174
case RISCV::SLLI_UW:
175175
case RISCV::FMV_W_X:
176176
case RISCV::FCVT_H_W:
177+
case RISCV::FCVT_H_W_INX:
177178
case RISCV::FCVT_H_WU:
179+
case RISCV::FCVT_H_WU_INX:
178180
case RISCV::FCVT_S_W:
181+
case RISCV::FCVT_S_W_INX:
179182
case RISCV::FCVT_S_WU:
183+
case RISCV::FCVT_S_WU_INX:
180184
case RISCV::FCVT_D_W:
185+
case RISCV::FCVT_D_W_INX:
181186
case RISCV::FCVT_D_WU:
187+
case RISCV::FCVT_D_WU_INX:
182188
if (Bits >= 32)
183189
break;
184190
return false;

‎llvm/test/CodeGen/RISCV/double-convert-strict.ll

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -777,11 +777,9 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind stri
777777
;
778778
; RV64IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:
779779
; RV64IZFINXZDINX: # %bb.0:
780-
; RV64IZFINXZDINX-NEXT: addiw a2, a0, 1
781-
; RV64IZFINXZDINX-NEXT: addi a0, a0, 1
782-
; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
783-
; RV64IZFINXZDINX-NEXT: sd a0, 0(a1)
784-
; RV64IZFINXZDINX-NEXT: mv a0, a2
780+
; RV64IZFINXZDINX-NEXT: addiw a0, a0, 1
781+
; RV64IZFINXZDINX-NEXT: fcvt.d.w a2, a0
782+
; RV64IZFINXZDINX-NEXT: sd a2, 0(a1)
785783
; RV64IZFINXZDINX-NEXT: ret
786784
;
787785
; RV32I-LABEL: fcvt_d_w_demanded_bits:

‎llvm/test/CodeGen/RISCV/double-convert.ll

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1459,11 +1459,9 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
14591459
;
14601460
; RV64IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:
14611461
; RV64IZFINXZDINX: # %bb.0:
1462-
; RV64IZFINXZDINX-NEXT: addiw a2, a0, 1
1463-
; RV64IZFINXZDINX-NEXT: addi a0, a0, 1
1464-
; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1465-
; RV64IZFINXZDINX-NEXT: sd a0, 0(a1)
1466-
; RV64IZFINXZDINX-NEXT: mv a0, a2
1462+
; RV64IZFINXZDINX-NEXT: addiw a0, a0, 1
1463+
; RV64IZFINXZDINX-NEXT: fcvt.d.w a2, a0
1464+
; RV64IZFINXZDINX-NEXT: sd a2, 0(a1)
14671465
; RV64IZFINXZDINX-NEXT: ret
14681466
;
14691467
; RV32I-LABEL: fcvt_d_w_demanded_bits:

‎llvm/test/CodeGen/RISCV/float-convert-strict.ll

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -645,11 +645,9 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind stri
645645
;
646646
; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits:
647647
; RV64IZFINX: # %bb.0:
648-
; RV64IZFINX-NEXT: addiw a2, a0, 1
649-
; RV64IZFINX-NEXT: addi a0, a0, 1
650-
; RV64IZFINX-NEXT: fcvt.s.w a0, a0
651-
; RV64IZFINX-NEXT: sw a0, 0(a1)
652-
; RV64IZFINX-NEXT: mv a0, a2
648+
; RV64IZFINX-NEXT: addiw a0, a0, 1
649+
; RV64IZFINX-NEXT: fcvt.s.w a2, a0
650+
; RV64IZFINX-NEXT: sw a2, 0(a1)
653651
; RV64IZFINX-NEXT: ret
654652
;
655653
; RV32I-LABEL: fcvt_s_w_demanded_bits:

‎llvm/test/CodeGen/RISCV/float-convert.ll

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1247,11 +1247,9 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
12471247
;
12481248
; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits:
12491249
; RV64IZFINX: # %bb.0:
1250-
; RV64IZFINX-NEXT: addiw a2, a0, 1
1251-
; RV64IZFINX-NEXT: addi a0, a0, 1
1252-
; RV64IZFINX-NEXT: fcvt.s.w a0, a0
1253-
; RV64IZFINX-NEXT: sw a0, 0(a1)
1254-
; RV64IZFINX-NEXT: mv a0, a2
1250+
; RV64IZFINX-NEXT: addiw a0, a0, 1
1251+
; RV64IZFINX-NEXT: fcvt.s.w a2, a0
1252+
; RV64IZFINX-NEXT: sw a2, 0(a1)
12551253
; RV64IZFINX-NEXT: ret
12561254
;
12571255
; RV32I-LABEL: fcvt_s_w_demanded_bits:

‎llvm/test/CodeGen/RISCV/half-convert-strict.ll

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1963,11 +1963,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) strictfp {
19631963
;
19641964
; RV64IZHINX-LABEL: fcvt_h_w_demanded_bits:
19651965
; RV64IZHINX: # %bb.0:
1966-
; RV64IZHINX-NEXT: addiw a2, a0, 1
1967-
; RV64IZHINX-NEXT: addi a0, a0, 1
1968-
; RV64IZHINX-NEXT: fcvt.h.w a0, a0
1969-
; RV64IZHINX-NEXT: sh a0, 0(a1)
1970-
; RV64IZHINX-NEXT: mv a0, a2
1966+
; RV64IZHINX-NEXT: addiw a0, a0, 1
1967+
; RV64IZHINX-NEXT: fcvt.h.w a2, a0
1968+
; RV64IZHINX-NEXT: sh a2, 0(a1)
19711969
; RV64IZHINX-NEXT: ret
19721970
;
19731971
; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
@@ -1993,11 +1991,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) strictfp {
19931991
;
19941992
; RV64IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
19951993
; RV64IZDINXZHINX: # %bb.0:
1996-
; RV64IZDINXZHINX-NEXT: addiw a2, a0, 1
1997-
; RV64IZDINXZHINX-NEXT: addi a0, a0, 1
1998-
; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
1999-
; RV64IZDINXZHINX-NEXT: sh a0, 0(a1)
2000-
; RV64IZDINXZHINX-NEXT: mv a0, a2
1994+
; RV64IZDINXZHINX-NEXT: addiw a0, a0, 1
1995+
; RV64IZDINXZHINX-NEXT: fcvt.h.w a2, a0
1996+
; RV64IZDINXZHINX-NEXT: sh a2, 0(a1)
20011997
; RV64IZDINXZHINX-NEXT: ret
20021998
;
20031999
; CHECK32-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:

‎llvm/test/CodeGen/RISCV/half-convert.ll

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -5760,11 +5760,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
57605760
;
57615761
; RV64IZHINX-LABEL: fcvt_h_w_demanded_bits:
57625762
; RV64IZHINX: # %bb.0:
5763-
; RV64IZHINX-NEXT: addiw a2, a0, 1
5764-
; RV64IZHINX-NEXT: addi a0, a0, 1
5765-
; RV64IZHINX-NEXT: fcvt.h.w a0, a0
5766-
; RV64IZHINX-NEXT: sh a0, 0(a1)
5767-
; RV64IZHINX-NEXT: mv a0, a2
5763+
; RV64IZHINX-NEXT: addiw a0, a0, 1
5764+
; RV64IZHINX-NEXT: fcvt.h.w a2, a0
5765+
; RV64IZHINX-NEXT: sh a2, 0(a1)
57685766
; RV64IZHINX-NEXT: ret
57695767
;
57705768
; RV32IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
@@ -5776,11 +5774,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
57765774
;
57775775
; RV64IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
57785776
; RV64IZDINXZHINX: # %bb.0:
5779-
; RV64IZDINXZHINX-NEXT: addiw a2, a0, 1
5780-
; RV64IZDINXZHINX-NEXT: addi a0, a0, 1
5781-
; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
5782-
; RV64IZDINXZHINX-NEXT: sh a0, 0(a1)
5783-
; RV64IZDINXZHINX-NEXT: mv a0, a2
5777+
; RV64IZDINXZHINX-NEXT: addiw a0, a0, 1
5778+
; RV64IZDINXZHINX-NEXT: fcvt.h.w a2, a0
5779+
; RV64IZDINXZHINX-NEXT: sh a2, 0(a1)
57845780
; RV64IZDINXZHINX-NEXT: ret
57855781
;
57865782
; RV32I-LABEL: fcvt_h_w_demanded_bits:

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