[InstCombine] Don't combine smul of i1 type constant one

Fixes: #59876

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D141214

Author: luxufan

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

@@ -4986,15 +4986,16 @@ Instruction *InstCombinerImpl::foldICmpWithCastOp(ICmpInst &ICmp) {
   return foldICmpWithZextOrSext(ICmp);
 }
 
-static bool isNeutralValue(Instruction::BinaryOps BinaryOp, Value *RHS) {
+static bool isNeutralValue(Instruction::BinaryOps BinaryOp, Value *RHS, bool IsSigned) {
   switch (BinaryOp) {
     default:
       llvm_unreachable("Unsupported binary op");
     case Instruction::Add:
     case Instruction::Sub:
       return match(RHS, m_Zero());
     case Instruction::Mul:
-      return match(RHS, m_One());
+      return !(RHS->getType()->isIntOrIntVectorTy(1) && IsSigned) &&
+             match(RHS, m_One());
   }
 }
 
@@ -5041,7 +5042,7 @@ bool InstCombinerImpl::OptimizeOverflowCheck(Instruction::BinaryOps BinaryOp,
   if (auto *LHSTy = dyn_cast<VectorType>(LHS->getType()))
     OverflowTy = VectorType::get(OverflowTy, LHSTy->getElementCount());
 
-  if (isNeutralValue(BinaryOp, RHS)) {
+  if (isNeutralValue(BinaryOp, RHS, IsSigned)) {
     Result = LHS;
     Overflow = ConstantInt::getFalse(OverflowTy);
     return true;

llvm/test/Transforms/InstCombine/smulo.ll

@@ -160,7 +160,7 @@ define <2 x i1> @v2i1_ov(<2 x i1> %x, <2 x i1> %y) {
 
 define i1 @i1_ov_by_one(i1 %x) {
 ; CHECK-LABEL: @i1_ov_by_one(
-; CHECK-NEXT:    ret i1 false
+; CHECK-NEXT:    ret i1 [[X:%.*]]
 ;
   %m = call {i1, i1} @llvm.smul.with.overflow.i1(i1 %x, i1 1)
   %ov = extractvalue {i1, i1} %m, 1
@@ -169,7 +169,7 @@ define i1 @i1_ov_by_one(i1 %x) {
 
 define <2 x i1> @v2i1_ov_by_one(<2 x i1> %x) {
 ; CHECK-LABEL: @v2i1_ov_by_one(
-; CHECK-NEXT:    ret <2 x i1> zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[X:%.*]]
 ;
   %m = call {<2 x i1>, <2 x i1>} @llvm.smul.with.overflow.v2i1(<2 x i1> %x, <2 x i1> <i1 1, i1 1>)
   %ov = extractvalue {<2 x i1>, <2 x i1>} %m, 1